Rev 105 | Rev 112 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1 | jermar | 1 | /* |
| 2 | * Copyright (C) 2001-2004 Jakub Jermar |
||
| 3 | * All rights reserved. |
||
| 4 | * |
||
| 5 | * Redistribution and use in source and binary forms, with or without |
||
| 6 | * modification, are permitted provided that the following conditions |
||
| 7 | * are met: |
||
| 8 | * |
||
| 9 | * - Redistributions of source code must retain the above copyright |
||
| 10 | * notice, this list of conditions and the following disclaimer. |
||
| 11 | * - Redistributions in binary form must reproduce the above copyright |
||
| 12 | * notice, this list of conditions and the following disclaimer in the |
||
| 13 | * documentation and/or other materials provided with the distribution. |
||
| 14 | * - The name of the author may not be used to endorse or promote products |
||
| 15 | * derived from this software without specific prior written permission. |
||
| 16 | * |
||
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
||
| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
||
| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
||
| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
||
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
||
| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
||
| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
||
| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
||
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
||
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||
| 27 | */ |
||
| 28 | |||
| 29 | #include <arch/pm.h> |
||
| 30 | #include <config.h> |
||
| 31 | #include <arch/types.h> |
||
| 32 | #include <typedefs.h> |
||
| 33 | #include <arch/interrupt.h> |
||
| 34 | #include <arch/asm.h> |
||
| 35 | #include <arch/context.h> |
||
| 36 | #include <panic.h> |
||
| 37 | |||
| 38 | /* |
||
| 11 | jermar | 39 | * Early ia32 configuration functions and data structures. |
| 1 | jermar | 40 | */ |
| 41 | |||
| 42 | /* |
||
| 43 | * We have no use for segmentation so we set up flat mode. In this |
||
| 44 | * mode, we use, for each privilege level, two segments spanning the |
||
| 45 | * whole memory. One is for code and one is for data. |
||
| 46 | */ |
||
| 47 | struct descriptor gdt[GDT_ITEMS] = { |
||
| 48 | /* NULL descriptor */ |
||
| 49 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
||
| 50 | /* KTEXT descriptor */ |
||
| 51 | { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 }, |
||
| 52 | /* KDATA descriptor */ |
||
| 53 | { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 }, |
||
| 54 | /* UTEXT descriptor */ |
||
| 55 | { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, |
||
| 56 | /* UDATA descriptor */ |
||
| 57 | { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, |
||
| 58 | /* TSS descriptor - set up will be completed later */ |
||
| 59 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } |
||
| 60 | }; |
||
| 61 | |||
| 62 | static struct idescriptor idt[IDT_ITEMS]; |
||
| 63 | |||
| 64 | static struct tss tss; |
||
| 65 | |||
| 66 | struct tss *tss_p = NULL; |
||
| 67 | |||
| 22 | jermar | 68 | /* gdtr is changed by kmp before next CPU is initialized */ |
| 105 | jermar | 69 | struct ptr_16_32 gdtr __attribute__ ((section ("K_DATA_START"))) = { .limit = sizeof(gdt), .base = KA2PA((__address) gdt) }; |
| 70 | struct ptr_16_32 idtr __attribute__ ((section ("K_DATA_START"))) = { .limit = sizeof(idt), .base = KA2PA((__address) idt) }; |
||
| 1 | jermar | 71 | |
| 72 | void gdt_setbase(struct descriptor *d, __address base) |
||
| 73 | { |
||
| 105 | jermar | 74 | d->base_0_15 = KA2PA(base) & 0xffff; |
| 75 | d->base_16_23 = (KA2PA(base) >> 16) & 0xff; |
||
| 76 | d->base_24_31 = (KA2PA(base) >> 24) & 0xff; |
||
| 110 | jermar | 77 | |
| 1 | jermar | 78 | } |
| 79 | |||
| 105 | jermar | 80 | void gdt_setlimit(struct descriptor *d, __u32 limit) |
| 1 | jermar | 81 | { |
| 82 | d->limit_0_15 = limit & 0xffff; |
||
| 83 | d->limit_16_19 = (limit >> 16) & 0xf; |
||
| 84 | } |
||
| 85 | |||
| 86 | void idt_setoffset(struct idescriptor *d, __address offset) |
||
| 87 | { |
||
| 105 | jermar | 88 | d->offset_0_15 = KA2PA(offset) & 0xffff; |
| 89 | d->offset_16_31 = KA2PA(offset) >> 16; |
||
| 1 | jermar | 90 | } |
| 91 | |||
| 92 | void tss_initialize(struct tss *t) |
||
| 93 | { |
||
| 94 | memsetb((__address) t, sizeof(struct tss), 0); |
||
| 95 | } |
||
| 96 | |||
| 97 | /* |
||
| 98 | * This function takes care of proper setup of IDT and IDTR. |
||
| 99 | */ |
||
| 100 | void idt_init(void) |
||
| 101 | { |
||
| 102 | struct idescriptor *d; |
||
| 103 | int i; |
||
| 104 | |||
| 105 | for (i = 0; i < IDT_ITEMS; i++) { |
||
| 106 | d = &idt[i]; |
||
| 107 | |||
| 108 | d->unused = 0; |
||
| 109 | d->selector = selector(KTEXT_DES); |
||
| 110 | |||
| 111 | d->access = AR_PRESENT | AR_INTERRUPT; /* masking interrupt */ |
||
| 112 | |||
| 113 | if (i == VECTOR_SYSCALL) { |
||
| 114 | /* |
||
| 115 | * The syscall interrupt gate must be calleable from userland. |
||
| 116 | */ |
||
| 117 | d->access |= DPL_USER; |
||
| 118 | } |
||
| 119 | |||
| 120 | idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size); |
||
| 121 | trap_register(i, null_interrupt); |
||
| 122 | } |
||
| 123 | trap_register(13, gp_fault); |
||
| 73 | vana | 124 | trap_register( 7, nm_fault); |
| 84 | vana | 125 | trap_register(12, ss_fault); |
| 1 | jermar | 126 | } |
| 127 | |||
| 128 | |||
| 129 | void pm_init(void) |
||
| 130 | { |
||
| 131 | struct descriptor *gdt_p = (struct descriptor *) gdtr.base; |
||
| 132 | |||
| 133 | /* |
||
| 134 | * Each CPU has its private GDT and TSS. |
||
| 135 | * All CPUs share one IDT. |
||
| 136 | */ |
||
| 137 | |||
| 138 | if (config.cpu_active == 1) { |
||
| 139 | idt_init(); |
||
| 140 | /* |
||
| 141 | * NOTE: bootstrap CPU has statically allocated TSS, because |
||
| 142 | * the heap hasn't been initialized so far. |
||
| 143 | */ |
||
| 144 | tss_p = &tss; |
||
| 145 | } |
||
| 146 | else { |
||
| 147 | tss_p = (struct tss *) malloc(sizeof(struct tss)); |
||
| 148 | if (!tss_p) |
||
| 68 | decky | 149 | panic("could not allocate TSS\n"); |
| 1 | jermar | 150 | } |
| 151 | |||
| 152 | tss_initialize(tss_p); |
||
| 153 | |||
| 154 | gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL; |
||
| 155 | gdt_p[TSS_DES].special = 1; |
||
| 156 | gdt_p[TSS_DES].granularity = 1; |
||
| 157 | |||
| 158 | gdt_setbase(&gdt_p[TSS_DES], (__address) tss_p); |
||
| 159 | gdt_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1); |
||
| 160 | |||
| 161 | /* |
||
| 162 | * As of this moment, the current CPU has its own GDT pointing |
||
| 163 | * to its own TSS. We just need to load the TR register. |
||
| 164 | */ |
||
| 165 | __asm__("ltr %0" : : "r" ((__u16) selector(TSS_DES))); |
||
| 166 | } |