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1 jermar 1
/*
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 * Copyright (C) 2001-2004 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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#include <arch/pm.h>
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#include <config.h>
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#include <arch/types.h>
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#include <typedefs.h>
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#include <arch/interrupt.h>
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#include <arch/asm.h>
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#include <arch/context.h>
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#include <panic.h>
167 jermar 37
#include <arch/mm/page.h>
814 palkovsky 38
#include <mm/slab.h>
195 vana 39
#include <memstr.h>
244 decky 40
#include <arch/boot/boot.h>
576 palkovsky 41
#include <interrupt.h>
1 jermar 42
 
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/*
11 jermar 44
 * Early ia32 configuration functions and data structures.
1 jermar 45
 */
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/*
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 * We have no use for segmentation so we set up flat mode. In this
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 * mode, we use, for each privilege level, two segments spanning the
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 * whole memory. One is for code and one is for data.
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 */
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struct descriptor gdt[GDT_ITEMS] = {
125 jermar 53
    /* NULL descriptor */
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    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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    /* KTEXT descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
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    /* KDATA descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
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    /* UTEXT descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
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    /* UDATA descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
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    /* TSS descriptor - set up will be completed later */
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    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1 jermar 65
};
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static struct idescriptor idt[IDT_ITEMS];
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static struct tss tss;
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struct tss *tss_p = NULL;
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22 jermar 73
/* gdtr is changed by kmp before next CPU is initialized */
693 decky 74
struct ptr_16_32 bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((__address) gdt) };
271 decky 75
struct ptr_16_32 gdtr = { .limit = sizeof(gdt), .base = (__address) gdt };
1 jermar 76
 
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void gdt_setbase(struct descriptor *d, __address base)
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{
125 jermar 79
    d->base_0_15 = base & 0xffff;
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    d->base_16_23 = ((base) >> 16) & 0xff;
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    d->base_24_31 = ((base) >> 24) & 0xff;
1 jermar 82
}
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105 jermar 84
void gdt_setlimit(struct descriptor *d, __u32 limit)
1 jermar 85
{
125 jermar 86
    d->limit_0_15 = limit & 0xffff;
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    d->limit_16_19 = (limit >> 16) & 0xf;
1 jermar 88
}
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void idt_setoffset(struct idescriptor *d, __address offset)
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{
112 jermar 92
    /*
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     * Offset is a linear address.
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     */
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    d->offset_0_15 = offset & 0xffff;
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    d->offset_16_31 = offset >> 16;
1 jermar 97
}
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void tss_initialize(struct tss *t)
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{
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    memsetb((__address) t, sizeof(struct tss), 0);
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}
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/*
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 * This function takes care of proper setup of IDT and IDTR.
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 */
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void idt_init(void)
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{
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    struct idescriptor *d;
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    int i;
125 jermar 111
 
1 jermar 112
    for (i = 0; i < IDT_ITEMS; i++) {
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        d = &idt[i];
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        d->unused = 0;
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        d->selector = selector(KTEXT_DES);
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        d->access = AR_PRESENT | AR_INTERRUPT;  /* masking interrupt */
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        if (i == VECTOR_SYSCALL) {
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            /*
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             * The syscall interrupt gate must be calleable from userland.
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             */
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            d->access |= DPL_USER;
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        }
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        idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
958 jermar 128
        exc_register(i, "undef", (iroutine) null_interrupt);
1 jermar 129
    }
958 jermar 130
    exc_register(13, "gp_fault", (iroutine) gp_fault);
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    exc_register( 7, "nm_fault", (iroutine) nm_fault);
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    exc_register(12, "ss_fault", (iroutine) ss_fault);
1019 vana 133
    exc_register(19, "simd_fp", (iroutine) simd_fp_exception);
1 jermar 134
}
135
 
136
 
144 vana 137
/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
141 vana 138
static void clean_IOPL_NT_flags(void)
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{
167 jermar 140
    asm
141 vana 141
    (
167 jermar 142
        "pushfl;"
141 vana 143
        "pop %%eax;"
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        "and $0xffff8fff,%%eax;"
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        "push %%eax;"
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        "popfl;"
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        :
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        :
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        :"%eax"
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    );
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}
152
 
144 vana 153
/* Clean AM(18) flag in CR0 register */
143 vana 154
static void clean_AM_flag(void)
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{
167 jermar 156
    asm
143 vana 157
    (
167 jermar 158
        "mov %%cr0,%%eax;"
143 vana 159
        "and $0xFFFBFFFF,%%eax;"
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        "mov %%eax,%%cr0;"
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        :
162
        :
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        :"%eax"
164
    );
165
}
141 vana 166
 
1 jermar 167
void pm_init(void)
168
{
271 decky 169
    struct descriptor *gdt_p = (struct descriptor *) gdtr.base;
170
    struct ptr_16_32 idtr;
1 jermar 171
 
172
    /*
232 jermar 173
     * Update addresses in GDT and IDT to their virtual counterparts.
174
     */
271 decky 175
    idtr.limit = sizeof(idt);
232 jermar 176
    idtr.base = (__address) idt;
177
    __asm__ volatile ("lgdt %0\n" : : "m" (gdtr));
178
    __asm__ volatile ("lidt %0\n" : : "m" (idtr)); 
179
 
180
    /*
1 jermar 181
     * Each CPU has its private GDT and TSS.
182
     * All CPUs share one IDT.
183
     */
184
 
185
    if (config.cpu_active == 1) {
186
        idt_init();
187
        /*
188
         * NOTE: bootstrap CPU has statically allocated TSS, because
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         * the heap hasn't been initialized so far.
190
         */
191
        tss_p = &tss;
192
    }
193
    else {
822 palkovsky 194
        tss_p = (struct tss *) malloc(sizeof(struct tss),FRAME_ATOMIC);
1 jermar 195
        if (!tss_p)
68 decky 196
            panic("could not allocate TSS\n");
1 jermar 197
    }
198
 
199
    tss_initialize(tss_p);
200
 
201
    gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
202
    gdt_p[TSS_DES].special = 1;
203
    gdt_p[TSS_DES].granularity = 1;
204
 
205
    gdt_setbase(&gdt_p[TSS_DES], (__address) tss_p);
206
    gdt_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1);
207
 
208
    /*
209
     * As of this moment, the current CPU has its own GDT pointing
210
     * to its own TSS. We just need to load the TR register.
211
     */
232 jermar 212
    __asm__ volatile ("ltr %0" : : "r" ((__u16) selector(TSS_DES)));
141 vana 213
 
144 vana 214
    clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels */
215
    clean_AM_flag();          /* Disable alignment check */
1 jermar 216
}