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| 1 | jermar | 1 | /* |
| 2 | * Copyright (C) 2001-2004 Jakub Jermar |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 1702 | cejka | 29 | /** @addtogroup ia32cpu ia32 |
| 30 | * @ingroup cpu |
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| 31 | * @{ |
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| 32 | */ |
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| 33 | /** @file |
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| 34 | */ |
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| 35 | |||
| 1 | jermar | 36 | #include <arch/cpu.h> |
| 37 | #include <arch/cpuid.h> |
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| 38 | #include <arch/pm.h> |
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| 39 | |||
| 40 | #include <arch.h> |
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| 41 | #include <arch/types.h> |
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| 42 | #include <print.h> |
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| 43 | #include <typedefs.h> |
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| 391 | jermar | 44 | #include <fpu_context.h> |
| 1 | jermar | 45 | |
| 16 | jermar | 46 | #include <arch/smp/apic.h> |
| 47 | |||
| 1 | jermar | 48 | /* |
| 49 | * Identification of CPUs. |
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| 50 | * Contains only non-MP-Specification specific SMP code. |
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| 51 | */ |
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| 52 | #define AMD_CPUID_EBX 0x68747541 |
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| 53 | #define AMD_CPUID_ECX 0x444d4163 |
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| 54 | #define AMD_CPUID_EDX 0x69746e65 |
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| 55 | |||
| 56 | #define INTEL_CPUID_EBX 0x756e6547 |
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| 57 | #define INTEL_CPUID_ECX 0x6c65746e |
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| 58 | #define INTEL_CPUID_EDX 0x49656e69 |
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| 59 | |||
| 141 | vana | 60 | |
| 1 | jermar | 61 | enum vendor { |
| 62 | VendorUnknown=0, |
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| 63 | VendorAMD, |
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| 64 | VendorIntel |
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| 65 | }; |
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| 66 | |||
| 67 | static char *vendor_str[] = { |
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| 68 | "Unknown Vendor", |
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| 69 | "AuthenticAMD", |
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| 70 | "GenuineIntel" |
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| 71 | }; |
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| 72 | |||
| 309 | palkovsky | 73 | void fpu_disable(void) |
| 58 | vana | 74 | { |
| 309 | palkovsky | 75 | __asm__ volatile ( |
| 58 | vana | 76 | "mov %%cr0,%%eax;" |
| 77 | "or $8,%%eax;" |
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| 78 | "mov %%eax,%%cr0;" |
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| 79 | : |
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| 80 | : |
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| 81 | :"%eax" |
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| 82 | ); |
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| 83 | } |
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| 84 | |||
| 309 | palkovsky | 85 | void fpu_enable(void) |
| 58 | vana | 86 | { |
| 309 | palkovsky | 87 | __asm__ volatile ( |
| 58 | vana | 88 | "mov %%cr0,%%eax;" |
| 89 | "and $0xffFFffF7,%%eax;" |
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| 90 | "mov %%eax,%%cr0;" |
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| 91 | : |
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| 92 | : |
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| 93 | :"%eax" |
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| 94 | ); |
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| 95 | } |
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| 96 | |||
| 1 | jermar | 97 | void cpu_arch_init(void) |
| 98 | { |
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| 1187 | jermar | 99 | cpuid_feature_info fi; |
| 100 | cpuid_extended_feature_info efi; |
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| 101 | cpu_info_t info; |
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| 102 | __u32 help = 0; |
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| 1019 | vana | 103 | |
| 15 | jermar | 104 | CPU->arch.tss = tss_p; |
| 1187 | jermar | 105 | CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((__u8 *) CPU->arch.tss); |
| 1019 | vana | 106 | |
| 1187 | jermar | 107 | CPU->fpu_owner = NULL; |
| 1019 | vana | 108 | |
| 109 | cpuid(1, &info); |
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| 110 | |||
| 1187 | jermar | 111 | fi.word = info.cpuid_edx; |
| 112 | efi.word = info.cpuid_ecx; |
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| 1019 | vana | 113 | |
| 1187 | jermar | 114 | if (fi.bits.fxsr) |
| 115 | fpu_fxsr(); |
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| 116 | else |
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| 117 | fpu_fsr(); |
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| 1019 | vana | 118 | |
| 1187 | jermar | 119 | if (fi.bits.sse) { |
| 120 | asm volatile ( |
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| 121 | "mov %%cr4,%0\n" |
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| 122 | "or %1,%0\n" |
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| 123 | "mov %0,%%cr4\n" |
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| 124 | : "+r" (help) |
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| 125 | : "i" (CR4_OSFXSR_MASK|(1<<10)) |
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| 126 | ); |
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| 127 | } |
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| 1 | jermar | 128 | } |
| 129 | |||
| 130 | void cpu_identify(void) |
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| 131 | { |
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| 132 | cpu_info_t info; |
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| 133 | |||
| 15 | jermar | 134 | CPU->arch.vendor = VendorUnknown; |
| 1 | jermar | 135 | if (has_cpuid()) { |
| 136 | cpuid(0, &info); |
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| 137 | |||
| 138 | /* |
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| 139 | * Check for AMD processor. |
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| 140 | */ |
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| 125 | jermar | 141 | if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) { |
| 15 | jermar | 142 | CPU->arch.vendor = VendorAMD; |
| 1 | jermar | 143 | } |
| 144 | |||
| 145 | /* |
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| 146 | * Check for Intel processor. |
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| 147 | */ |
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| 125 | jermar | 148 | if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) { |
| 15 | jermar | 149 | CPU->arch.vendor = VendorIntel; |
| 1 | jermar | 150 | } |
| 151 | |||
| 152 | cpuid(1, &info); |
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| 15 | jermar | 153 | CPU->arch.family = (info.cpuid_eax>>8)&0xf; |
| 154 | CPU->arch.model = (info.cpuid_eax>>4)&0xf; |
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| 155 | CPU->arch.stepping = (info.cpuid_eax>>0)&0xf; |
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| 1 | jermar | 156 | } |
| 157 | } |
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| 158 | |||
| 22 | jermar | 159 | void cpu_print_report(cpu_t* m) |
| 1 | jermar | 160 | { |
| 161 | printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n", |
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| 162 | m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping, |
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| 163 | m->frequency_mhz); |
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| 164 | } |
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| 1702 | cejka | 165 | |
| 166 | /** @} |
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| 167 | */ |
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| 168 |