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1 jermar 1
/*
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 * Copyright (C) 2001-2004 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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1702 cejka 29
 /** @addtogroup ia32  
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 * @{
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 */
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/** @file
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 */
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1 jermar 35
#ifndef __APIC_H__
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#define __APIC_H__
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#include <arch/types.h>
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#include <cpu.h>
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41
#define FIXED       (0<<0)
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#define LOPRI       (1<<0)
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515 jermar 44
#define APIC_ID_COUNT   16
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1 jermar 46
/* local APIC macros */
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#define IPI_INIT    0
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#define IPI_STARTUP 0
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513 jermar 50
/** Delivery modes. */
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#define DELMOD_FIXED    0x0
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#define DELMOD_LOWPRI   0x1
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#define DELMOD_SMI  0x2
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/* 0x3 reserved */
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#define DELMOD_NMI  0x4
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#define DELMOD_INIT 0x5
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#define DELMOD_STARTUP  0x6
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#define DELMOD_EXTINT   0x7
1 jermar 59
 
513 jermar 60
/** Destination modes. */
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#define DESTMOD_PHYS    0x0
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#define DESTMOD_LOGIC   0x1
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/** Trigger Modes. */
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#define TRIGMOD_EDGE    0x0
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#define TRIGMOD_LEVEL   0x1
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/** Levels. */
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#define LEVEL_DEASSERT  0x0
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#define LEVEL_ASSERT    0x1
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/** Destination Shorthands. */
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#define SHORTHAND_NONE      0x0
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#define SHORTHAND_SELF      0x1
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#define SHORTHAND_ALL_INCL  0x2
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#define SHORTHAND_ALL_EXCL  0x3
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/** Interrupt Input Pin Polarities. */
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#define POLARITY_HIGH   0x0
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#define POLARITY_LOW    0x1
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514 jermar 82
/** Divide Values. (Bit 2 is always 0) */
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#define DIVIDE_2    0x0
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#define DIVIDE_4    0x1
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#define DIVIDE_8    0x2
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#define DIVIDE_16   0x3
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#define DIVIDE_32   0x8
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#define DIVIDE_64   0x9
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#define DIVIDE_128  0xa
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#define DIVIDE_1    0xb
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/** Timer Modes. */
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#define TIMER_ONESHOT   0x0
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#define TIMER_PERIODIC  0x1
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515 jermar 96
/** Delivery status. */
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#define DELIVS_IDLE 0x0
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#define DELIVS_PENDING  0x1
1 jermar 99
 
515 jermar 100
/** Destination masks. */
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#define DEST_ALL    0xff
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672 jermar 103
/** Dest format models. */
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#define MODEL_FLAT  0xf
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#define MODEL_CLUSTER   0x0
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513 jermar 107
/** Interrupt Command Register. */
1 jermar 108
#define ICRlo       (0x300/sizeof(__u32))
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#define ICRhi       (0x310/sizeof(__u32))
513 jermar 110
struct icr {
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    union {
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        __u32 lo;
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        struct {
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            __u8 vector;            /**< Interrupt Vector. */
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            unsigned delmod : 3;        /**< Delivery Mode. */
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            unsigned destmod : 1;       /**< Destination Mode. */
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            unsigned delivs : 1;        /**< Delivery status (RO). */
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            unsigned : 1;           /**< Reserved. */
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            unsigned level : 1;     /**< Level. */
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            unsigned trigger_mode : 1;  /**< Trigger Mode. */
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            unsigned : 2;           /**< Reserved. */
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            unsigned shorthand : 2;     /**< Destination Shorthand. */
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            unsigned : 12;          /**< Reserved. */
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        } __attribute__ ((packed));
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    };
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    union {
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        __u32 hi;
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        struct {
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            unsigned : 24;          /**< Reserved. */
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            __u8 dest;          /**< Destination field. */
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        } __attribute__ ((packed));
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    };
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} __attribute__ ((packed));
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typedef struct icr icr_t;
1 jermar 135
 
1251 jermar 136
/* End Of Interrupt. */
1 jermar 137
#define EOI     (0x0b0/sizeof(__u32))
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514 jermar 139
/** Error Status Register. */
1 jermar 140
#define ESR     (0x280/sizeof(__u32))
514 jermar 141
union esr {
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    __u32 value;
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    __u8 err_bitmap;
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    struct {
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        unsigned send_checksum_error : 1;
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        unsigned receive_checksum_error : 1;
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        unsigned send_accept_error : 1;
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        unsigned receive_accept_error : 1;
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        unsigned : 1;
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        unsigned send_illegal_vector : 1;
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        unsigned received_illegal_vector : 1;
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        unsigned illegal_register_address : 1;
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        unsigned : 24;
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    } __attribute__ ((packed));
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};
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typedef union esr esr_t;
1 jermar 157
 
158
/* Task Priority Register */
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#define TPR     (0x080/sizeof(__u32))
750 jermar 160
union tpr {
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    __u32 value;
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    struct {
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        unsigned pri_sc : 4;        /**< Task Priority Sub-Class. */
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        unsigned pri : 4;       /**< Task Priority. */
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    } __attribute__ ((packed));
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};
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typedef union tpr tpr_t;
1 jermar 168
 
513 jermar 169
/** Spurious-Interrupt Vector Register. */
1 jermar 170
#define SVR     (0x0f0/sizeof(__u32))
513 jermar 171
union svr {
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    __u32 value;
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    struct {
750 jermar 174
        __u8 vector;            /**< Spurious Vector. */
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        unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable. */
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        unsigned focus_checking : 1;    /**< Focus Processor Checking. */
513 jermar 177
        unsigned : 22;          /**< Reserved. */
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    } __attribute__ ((packed));
179
};
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typedef union svr svr_t;
1 jermar 181
 
514 jermar 182
/** Time Divide Configuration Register. */
1 jermar 183
#define TDCR        (0x3e0/sizeof(__u32))
514 jermar 184
union tdcr {
185
    __u32 value;
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    struct {
187
        unsigned div_value : 4;     /**< Divide Value, bit 2 is always 0. */
188
        unsigned : 28;          /**< Reserved. */
189
    } __attribute__ ((packed));
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};
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typedef union tdcr tdcr_t;
1 jermar 192
 
193
/* Initial Count Register for Timer */
194
#define ICRT        (0x380/sizeof(__u32))
195
 
196
/* Current Count Register for Timer */
197
#define CCRT        (0x390/sizeof(__u32))
198
 
513 jermar 199
/** LVT Timer register. */
1 jermar 200
#define LVT_Tm      (0x320/sizeof(__u32))
513 jermar 201
union lvt_tm {
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    __u32 value;
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    struct {
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        __u8 vector;        /**< Local Timer Interrupt vector. */
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        unsigned : 4;       /**< Reserved. */
206
        unsigned delivs : 1;    /**< Delivery status (RO). */
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        unsigned : 3;       /**< Reserved. */
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        unsigned masked : 1;    /**< Interrupt Mask. */
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        unsigned mode : 1;  /**< Timer Mode. */
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        unsigned : 14;      /**< Reserved. */
211
    } __attribute__ ((packed));
212
};
213
typedef union lvt_tm lvt_tm_t;
214
 
215
/** LVT LINT registers. */
1 jermar 216
#define LVT_LINT0   (0x350/sizeof(__u32))
217
#define LVT_LINT1   (0x360/sizeof(__u32))
513 jermar 218
union lvt_lint {
219
    __u32 value;
220
    struct {
221
        __u8 vector;            /**< LINT Interrupt vector. */
222
        unsigned delmod : 3;        /**< Delivery Mode. */
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        unsigned : 1;           /**< Reserved. */
224
        unsigned delivs : 1;        /**< Delivery status (RO). */
225
        unsigned intpol : 1;        /**< Interrupt Input Pin Polarity. */
226
        unsigned irr : 1;       /**< Remote IRR (RO). */
227
        unsigned trigger_mode : 1;  /**< Trigger Mode. */
228
        unsigned masked : 1;        /**< Interrupt Mask. */
229
        unsigned : 15;          /**< Reserved. */
230
    } __attribute__ ((packed));
231
};
232
typedef union lvt_lint lvt_lint_t;
233
 
234
/** LVT Error register. */
1 jermar 235
#define LVT_Err     (0x370/sizeof(__u32))
513 jermar 236
union lvt_error {
237
    __u32 value;
238
    struct {
239
        __u8 vector;        /**< Local Timer Interrupt vector. */
240
        unsigned : 4;       /**< Reserved. */
241
        unsigned delivs : 1;    /**< Delivery status (RO). */
242
        unsigned : 3;       /**< Reserved. */
243
        unsigned masked : 1;    /**< Interrupt Mask. */
244
        unsigned : 15;      /**< Reserved. */
245
    } __attribute__ ((packed));
246
};
247
typedef union lvt_error lvt_error_t;
248
 
514 jermar 249
/** Local APIC ID Register. */
1 jermar 250
#define L_APIC_ID   (0x020/sizeof(__u32))
515 jermar 251
union l_apic_id {
514 jermar 252
    __u32 value;
253
    struct {
254
        unsigned : 24;      /**< Reserved. */
255
        __u8 apic_id;       /**< Local APIC ID. */
256
    } __attribute__ ((packed));
257
};
515 jermar 258
typedef union l_apic_id l_apic_id_t;
1 jermar 259
 
1251 jermar 260
/** Local APIC Version Register */
27 jermar 261
#define LAVR        (0x030/sizeof(__u32))
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#define LAVR_Mask   0xff
263
#define is_local_apic(x)    (((x)&LAVR_Mask&0xf0)==0x1)
264
#define is_82489DX_apic(x)  ((((x)&LAVR_Mask&0xf0)==0x0))
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#define is_local_xapic(x)   (((x)&LAVR_Mask)==0x14)
266
 
672 jermar 267
/** Logical Destination Register. */
268
#define  LDR        (0x0d0/sizeof(__u32))
269
union ldr {
270
    __u32 value;
271
    struct {
1251 jermar 272
        unsigned : 24;      /**< Reserved. */
672 jermar 273
        __u8 id;        /**< Logical APIC ID. */
274
    } __attribute__ ((packed));
275
};
276
typedef union ldr ldr_t;
277
 
278
/** Destination Format Register. */
279
#define DFR     (0x0e0/sizeof(__u32))
280
union dfr {
281
    __u32 value;
282
    struct {
283
        unsigned : 28;      /**< Reserved, all ones. */
284
        unsigned model : 4; /**< Model. */
285
    } __attribute__ ((packed));
286
};
287
typedef union dfr dfr_t;
288
 
1 jermar 289
/* IO APIC */
290
#define IOREGSEL    (0x00/sizeof(__u32))
291
#define IOWIN       (0x10/sizeof(__u32))
292
 
293
#define IOAPICID    0x00
294
#define IOAPICVER   0x01
295
#define IOAPICARB   0x02
296
#define IOREDTBL    0x10
297
 
514 jermar 298
/** I/O Register Select Register. */
299
union io_regsel {
300
    __u32 value;
301
    struct {
302
        __u8 reg_addr;      /**< APIC Register Address. */
303
        unsigned : 24;      /**< Reserved. */
304
    } __attribute__ ((packed));
305
};
306
typedef union io_regsel io_regsel_t;
307
 
512 jermar 308
/** I/O Redirection Register. */
309
struct io_redirection_reg {
310
    union {
311
        __u32 lo;
312
        struct {
513 jermar 313
            __u8 intvec;            /**< Interrupt Vector. */
512 jermar 314
            unsigned delmod : 3;        /**< Delivery Mode. */
315
            unsigned destmod : 1;       /**< Destination mode. */
316
            unsigned delivs : 1;        /**< Delivery status (RO). */
317
            unsigned intpol : 1;        /**< Interrupt Input Pin Polarity. */
318
            unsigned irr : 1;       /**< Remote IRR (RO). */
319
            unsigned trigger_mode : 1;  /**< Trigger Mode. */
320
            unsigned masked : 1;        /**< Interrupt Mask. */
321
            unsigned : 15;          /**< Reserved. */
513 jermar 322
        } __attribute__ ((packed));
512 jermar 323
    };
324
    union {
325
        __u32 hi;
326
        struct {
327
            unsigned : 24;          /**< Reserved. */
1251 jermar 328
            __u8 dest : 8;          /**< Destination Field. */
513 jermar 329
        } __attribute__ ((packed));
512 jermar 330
    };
331
 
332
} __attribute__ ((packed));
333
typedef struct io_redirection_reg io_redirection_reg_t;
334
 
515 jermar 335
 
336
/** IO APIC Identification Register. */
337
union io_apic_id {
338
    __u32 value;
339
    struct {
340
        unsigned : 24;      /**< Reserved. */
341
        unsigned apic_id : 4;   /**< IO APIC ID. */
342
        unsigned : 4;       /**< Reserved. */
343
    } __attribute__ ((packed));
344
};
345
typedef union io_apic_id io_apic_id_t;
346
 
1 jermar 347
extern volatile __u32 *l_apic;
348
extern volatile __u32 *io_apic;
349
 
350
extern __u32 apic_id_mask;
351
 
352
extern void apic_init(void);
353
 
354
extern void l_apic_init(void);
355
extern void l_apic_eoi(void);
5 jermar 356
extern int l_apic_broadcast_custom_ipi(__u8 vector);
1 jermar 357
extern int l_apic_send_init_ipi(__u8 apicid);
358
extern void l_apic_debug(void);
81 jermar 359
extern __u8 l_apic_id(void);
1 jermar 360
 
361
extern __u32 io_apic_read(__u8 address);
362
extern void io_apic_write(__u8 address , __u32 x);
514 jermar 363
extern void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags);
1 jermar 364
extern void io_apic_disable_irqs(__u16 irqmask);
365
extern void io_apic_enable_irqs(__u16 irqmask);
366
 
367
#endif
1702 cejka 368
 
369
 /** @}
370
 */
371