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<?xml version="1.0" encoding="UTF-8"?>
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<chapter id="architecture"><?dbhtml filename="arch.html"?>
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    <title>Architecture overview</title>
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    <section>
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        <title>Scheme</title>
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        <para>
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            <mediaobject id="arch1">
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                <imageobject role="html">
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                    <imagedata format="PNG" fileref="images/arch1.png"/>
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                </imageobject>
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                <imageobject role="fop">
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                    <imagedata format="SVG" fileref="images.vector/arch1.svg" />
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                </imageobject>
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            </mediaobject>
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        </para>
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    </section>
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    <section>
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        <title>Monolithic microkernel</title>
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        <para>
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            Though HelenOS was initially planned as a microkernel, we where trying to avoid several issues, connected
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            with microkernels, such as much higher overhead during memory management and hardware operations. For this reason
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            some of the subsytems, that are to be implmented as servers in classic microkernel design, where implemented
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            as a part of kernel, thus minimizing this overhead.
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        </para>
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        <formalpara>
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        <title>Memory management</title>
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        <para>
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            Unlike the classic microkernel, HelenOS has all its memory management functionality in the kernel, available to the memory
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            management server via the set of syscalls.
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        </para>
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        </formalpara>
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        <formalpara>
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        <title>Kernel device drivers</title>
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        <para>
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            HelenOS kernel has some of the very basic device drivers
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            <itemizedlist>
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            <listitem>ACPI</listitem>
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            <listitem>APIC</listitem>
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            <listitem>SMP configuration</listitem>
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            <listitem>System clock</listitem>
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            <listitem>Interrupt controllers</listitem>
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            <listitem>Console</listitem>
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            <listitem>VESA &amp; frame buffer</listitem>
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            </itemizedlist>
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        </para>
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        </formalpara>
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    </section>
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    <section>
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        <title>Kernel primitives</title>
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        <para>
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        <termdef><glossterm>Thread</glossterm> is the basic execution primitive.</termdef>
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        </para>
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        <para>
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        <termdef><glossterm>Thread context</glossterm> represents state of the <emphasis>thread</emphasis>. Contains registers state, FPU state, stack(s).</termdef>
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        </para>
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        <para>
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        <termdef><glossterm>Task</glossterm> </termdef>
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        </para>
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        <para>
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        <termdef>
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            <glossterm>Address space area</glossterm> is a mutually disjunctive range of memory with the code, stack and data.
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        </termdef>
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        </para>
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        <para>
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        <termdef>
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            <glossterm>Address space</glossterm> is a aggregating entity for address space areas, connecting them to the task.
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        </termdef>
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        </para>             1
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    </section>
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    <section>
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        <title>IPC</title>
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        <para>
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            Due to the high intertask communication traffic, IPC becomes critical subsystem for microkernels, putting high demands on the
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            speed, latency and reliability of IPC model and implementation. HelenOS IPC is designed in analogy with telephone communication.
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            Each task has an <emphasis>answerbox</emphasis> and a set of <emphasis>phones</emphasis> to call another tasks' answerboxes. Communication
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            is possible after the link establishment, and can be either <emphasis>asynchronious</emphasis> or <emphasis>synchronious</emphasis>.
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         </para>
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    </section>
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    <section>
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        <para>Task ID - unique 64 bit number. Used for syscalls.</para>
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        <para>Contains threads</para>
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        <para>Address space is created per task</para>
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        <para>Memory mapping is per task</para>
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        <para>Context per thread. (Note 2 stacks on IA64).</para>
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        <para>IPC answer box associated per task</para>
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        <title>Memory management</title>
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        <para>
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        Zones - linked list (not many zones, so we can afford it. Can be replaced with B-tree in the future)
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        Number of zones depends on HW tables. Describe zone allocation/deallocation algoritm
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        </para>
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        <para>Page tables. 4 level hierarchical and hash directly supported. B+ Tree can be implemented.</para>
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        <para>For paging there is an abstract layer</para>
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        <para>TLB shootdown implementation (update TLB upon mapping update/remove).
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        TLB shootdown ASID/ASID:PAGE/ALL.
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        TLB shootdown requests can come in asynchroniously
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        so there is a cache of TLB shootdown requests. Upon cache overflow TLB shootdown ALL is executed</para>
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        <para>
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            Address spaces. Address space area (B+ tree). Only for uspace. Set of syscalls (shrink/extend etc).
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            Special address space area type - device - prohibits shrink/extend syscalls to call on it.
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            Address space has link to mapping tables (hierarchical - per Address space, hash - global tables).
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        </para>
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    </section>
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</chapter>
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