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/*
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 * Copyright (c) 2007 Pavel Jancik
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup libcarm32
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 * @{
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 */
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/** @file
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 *  @brief Syscall routine.
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 */
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#include <libc.h>
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/** Syscall routine.
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 *
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 *  Stores p1-p4, id to r0-r4 registers and calls <code>swi</code>
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 *  instruction. Returned value is read from r0 register.
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 *
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 *  @param p1 Parameter 1.
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 *  @param p2 Parameter 2.
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 *  @param p3 Parameter 3.
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 *  @param p4 Parameter 4.
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 *  @param id Number of syscall.
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 *
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 *  @return Syscall return value.
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 */
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sysarg_t __syscall(const sysarg_t p1, const sysarg_t p2, const sysarg_t p3,
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    const sysarg_t p4, const syscall_t id)
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{
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    register sysarg_t __arm_reg_r0 asm("r0") = p1;
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    register sysarg_t __arm_reg_r1 asm("r1") = p2;
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    register sysarg_t __arm_reg_r2 asm("r2") = p3;
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    register sysarg_t __arm_reg_r3 asm("r3") = p4;
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    register sysarg_t __arm_reg_r4 asm("r4") = id;
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    asm volatile ( "swi"
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        : "=r" (__arm_reg_r0)
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        : "r"  (__arm_reg_r0),
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          "r"  (__arm_reg_r1),
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          "r"  (__arm_reg_r2),
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          "r"  (__arm_reg_r3),
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          "r"  (__arm_reg_r4)
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    );
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    return __arm_reg_r0;
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}
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/** @}
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 */