Rev 2054 | Rev 2089 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1903 | jermar | 1 | /* |
| 2071 | jermar | 2 | * Copyright (c) 2006 Jakub Jermar |
| 1903 | jermar | 3 | * All rights reserved. |
| 4 | * |
||
| 5 | * Redistribution and use in source and binary forms, with or without |
||
| 6 | * modification, are permitted provided that the following conditions |
||
| 7 | * are met: |
||
| 8 | * |
||
| 9 | * - Redistributions of source code must retain the above copyright |
||
| 10 | * notice, this list of conditions and the following disclaimer. |
||
| 11 | * - Redistributions in binary form must reproduce the above copyright |
||
| 12 | * notice, this list of conditions and the following disclaimer in the |
||
| 13 | * documentation and/or other materials provided with the distribution. |
||
| 14 | * - The name of the author may not be used to endorse or promote products |
||
| 15 | * derived from this software without specific prior written permission. |
||
| 16 | * |
||
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
||
| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
||
| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
||
| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
||
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
||
| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
||
| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
||
| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
||
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
||
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||
| 27 | */ |
||
| 28 | |||
| 29 | /** @addtogroup sparc64 |
||
| 30 | * @{ |
||
| 31 | */ |
||
| 32 | /** @file |
||
| 33 | */ |
||
| 34 | |||
| 35 | #include <smp/ipi.h> |
||
| 1904 | jermar | 36 | #include <cpu.h> |
| 37 | #include <arch/cpu.h> |
||
| 38 | #include <arch/asm.h> |
||
| 39 | #include <config.h> |
||
| 40 | #include <mm/tlb.h> |
||
| 41 | #include <arch/interrupt.h> |
||
| 42 | #include <arch/trap/interrupt.h> |
||
| 43 | #include <arch/barrier.h> |
||
| 44 | #include <preemption.h> |
||
| 45 | #include <time/delay.h> |
||
| 46 | #include <panic.h> |
||
| 1903 | jermar | 47 | |
| 1904 | jermar | 48 | /** Invoke function on another processor. |
| 49 | * |
||
| 50 | * Currently, only functions without arguments are supported. |
||
| 51 | * Supporting more arguments in the future should be no big deal. |
||
| 52 | * |
||
| 53 | * Interrupts must be disabled prior to this call. |
||
| 54 | * |
||
| 55 | * @param mid MID of the target processor. |
||
| 56 | * @param func Function to be invoked. |
||
| 57 | */ |
||
| 58 | static void cross_call(int mid, void (* func)(void)) |
||
| 59 | { |
||
| 60 | uint64_t status; |
||
| 61 | bool done; |
||
| 62 | |||
| 63 | /* |
||
| 2048 | jermar | 64 | * This function might enable interrupts for a while. |
| 1904 | jermar | 65 | * In order to prevent migration to another processor, |
| 66 | * we explicitly disable preemption. |
||
| 67 | */ |
||
| 68 | |||
| 69 | preemption_disable(); |
||
| 70 | |||
| 71 | status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0); |
||
| 72 | if (status & INTR_DISPATCH_STATUS_BUSY) |
||
| 73 | panic("Interrupt Dispatch Status busy bit set\n"); |
||
| 74 | |||
| 75 | do { |
||
| 2054 | jermar | 76 | asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t) |
| 77 | func); |
||
| 1904 | jermar | 78 | asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_1, 0); |
| 79 | asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_2, 0); |
||
| 2054 | jermar | 80 | asi_u64_write(ASI_UDB_INTR_W, (mid << |
| 81 | INTR_VEC_DISPATCH_MID_SHIFT) | ASI_UDB_INTR_W_DISPATCH, |
||
| 82 | 0); |
||
| 1904 | jermar | 83 | |
| 84 | membar(); |
||
| 85 | |||
| 86 | do { |
||
| 87 | status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0); |
||
| 88 | } while (status & INTR_DISPATCH_STATUS_BUSY); |
||
| 89 | |||
| 90 | done = !(status & INTR_DISPATCH_STATUS_NACK); |
||
| 91 | if (!done) { |
||
| 92 | /* |
||
| 93 | * Prevent deadlock. |
||
| 94 | */ |
||
| 95 | (void) interrupts_enable(); |
||
| 96 | delay(20 + (tick_read() & 0xff)); |
||
| 97 | (void) interrupts_disable(); |
||
| 98 | } |
||
| 99 | } while (done); |
||
| 100 | |||
| 101 | preemption_enable(); |
||
| 102 | } |
||
| 103 | |||
| 104 | /* |
||
| 105 | * Deliver IPI to all processors except the current one. |
||
| 106 | * |
||
| 107 | * The sparc64 architecture does not support any group addressing |
||
| 108 | * which is found, for instance, on ia32 and amd64. Therefore we |
||
| 109 | * need to simulate the broadcast by sending the message to |
||
| 110 | * all target processors step by step. |
||
| 111 | * |
||
| 112 | * We assume that interrupts are disabled. |
||
| 113 | * |
||
| 114 | * @param ipi IPI number. |
||
| 115 | */ |
||
| 1903 | jermar | 116 | void ipi_broadcast_arch(int ipi) |
| 117 | { |
||
| 1904 | jermar | 118 | int i; |
| 119 | |||
| 120 | void (* func)(void); |
||
| 121 | |||
| 122 | switch (ipi) { |
||
| 123 | case IPI_TLB_SHOOTDOWN: |
||
| 124 | func = tlb_shootdown_ipi_recv; |
||
| 125 | break; |
||
| 126 | default: |
||
| 127 | panic("Unknown IPI (%d).\n", ipi); |
||
| 128 | break; |
||
| 129 | } |
||
| 130 | |||
| 131 | /* |
||
| 132 | * As long as we don't support hot-plugging |
||
| 133 | * or hot-unplugging of CPUs, we can walk |
||
| 134 | * the cpus array and read processor's MID |
||
| 135 | * without locking. |
||
| 136 | */ |
||
| 137 | |||
| 138 | for (i = 0; i < config.cpu_active; i++) { |
||
| 139 | if (&cpus[i] == CPU) |
||
| 140 | continue; /* skip the current CPU */ |
||
| 141 | |||
| 142 | cross_call(cpus[i].arch.mid, func); |
||
| 143 | } |
||
| 1903 | jermar | 144 | } |
| 145 | |||
| 146 | /** @} |
||
| 147 | */ |