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570 jermar 1
/*
2071 jermar 2
 * Copyright (c) 2005 Jakub Jermar
570 jermar 3
 * All rights reserved.
4
 *
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
7
 * are met:
8
 *
9
 * - Redistributions of source code must retain the above copyright
10
 *   notice, this list of conditions and the following disclaimer.
11
 * - Redistributions in binary form must reproduce the above copyright
12
 *   notice, this list of conditions and the following disclaimer in the
13
 *   documentation and/or other materials provided with the distribution.
14
 * - The name of the author may not be used to endorse or promote products
15
 *   derived from this software without specific prior written permission.
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
28
 
1792 jermar 29
/** @addtogroup sparc64mm  
1702 cejka 30
 * @{
31
 */
32
/** @file
33
 */
34
 
570 jermar 35
#include <arch/mm/tlb.h>
36
#include <mm/tlb.h>
1851 jermar 37
#include <mm/as.h>
38
#include <mm/asid.h>
619 jermar 39
#include <arch/mm/frame.h>
40
#include <arch/mm/page.h>
41
#include <arch/mm/mmu.h>
1851 jermar 42
#include <arch/interrupt.h>
1870 jermar 43
#include <interrupt.h>
1851 jermar 44
#include <arch.h>
570 jermar 45
#include <print.h>
617 jermar 46
#include <arch/types.h>
619 jermar 47
#include <config.h>
630 jermar 48
#include <arch/trap/trap.h>
1880 jermar 49
#include <arch/trap/exception.h>
863 jermar 50
#include <panic.h>
873 jermar 51
#include <arch/asm.h>
894 jermar 52
 
1891 jermar 53
#ifdef CONFIG_TSB
54
#include <arch/mm/tsb.h>
55
#endif
56
 
3672 jermar 57
static void dtlb_pte_copy(pte_t *, index_t, bool);
58
static void itlb_pte_copy(pte_t *, index_t);
59
static void do_fast_instruction_access_mmu_miss_fault(istate_t *, const char *);
60
static void do_fast_data_access_mmu_miss_fault(istate_t *, tlb_tag_access_reg_t,
61
    const char *);
62
static void do_fast_data_access_protection_fault(istate_t *,
63
    tlb_tag_access_reg_t, const char *);
1851 jermar 64
 
873 jermar 65
char *context_encoding[] = {
66
    "Primary",
67
    "Secondary",
68
    "Nucleus",
69
    "Reserved"
70
};
71
 
570 jermar 72
void tlb_arch_init(void)
73
{
1793 jermar 74
    /*
1905 jermar 75
     * Invalidate all non-locked DTLB and ITLB entries.
1793 jermar 76
     */
1905 jermar 77
    tlb_invalidate_all();
1946 jermar 78
 
79
    /*
80
     * Clear both SFSRs.
81
     */
82
    dtlb_sfsr_write(0);
83
    itlb_sfsr_write(0);
897 jermar 84
}
873 jermar 85
 
897 jermar 86
/** Insert privileged mapping into DMMU TLB.
87
 *
3672 jermar 88
 * @param page      Virtual page address.
89
 * @param frame     Physical frame address.
90
 * @param pagesize  Page size.
91
 * @param locked    True for permanent mappings, false otherwise.
92
 * @param cacheable True if the mapping is cacheable, false otherwise.
897 jermar 93
 */
2141 jermar 94
void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize,
95
    bool locked, bool cacheable)
897 jermar 96
{
97
    tlb_tag_access_reg_t tag;
98
    tlb_data_t data;
99
    page_address_t pg;
100
    frame_address_t fr;
873 jermar 101
 
897 jermar 102
    pg.address = page;
103
    fr.address = frame;
873 jermar 104
 
3672 jermar 105
    tag.context = ASID_KERNEL;
894 jermar 106
    tag.vpn = pg.vpn;
107
 
108
    dtlb_tag_access_write(tag.value);
109
 
110
    data.value = 0;
111
    data.v = true;
897 jermar 112
    data.size = pagesize;
894 jermar 113
    data.pfn = fr.pfn;
897 jermar 114
    data.l = locked;
115
    data.cp = cacheable;
2009 jermar 116
#ifdef CONFIG_VIRT_IDX_DCACHE
897 jermar 117
    data.cv = cacheable;
2009 jermar 118
#endif /* CONFIG_VIRT_IDX_DCACHE */
894 jermar 119
    data.p = true;
120
    data.w = true;
1868 jermar 121
    data.g = false;
894 jermar 122
 
123
    dtlb_data_in_write(data.value);
570 jermar 124
}
125
 
1852 jermar 126
/** Copy PTE to TLB.
127
 *
3672 jermar 128
 * @param t         Page Table Entry to be copied.
129
 * @param index     Zero if lower 8K-subpage, one if higher 8K-subpage.
130
 * @param ro        If true, the entry will be created read-only, regardless
131
 *          of its w field.
1852 jermar 132
 */
2141 jermar 133
void dtlb_pte_copy(pte_t *t, index_t index, bool ro)
1851 jermar 134
{
1852 jermar 135
    tlb_tag_access_reg_t tag;
136
    tlb_data_t data;
137
    page_address_t pg;
138
    frame_address_t fr;
139
 
2141 jermar 140
    pg.address = t->page + (index << MMU_PAGE_WIDTH);
141
    fr.address = t->frame + (index << MMU_PAGE_WIDTH);
1852 jermar 142
 
143
    tag.value = 0;
144
    tag.context = t->as->asid;
145
    tag.vpn = pg.vpn;
2141 jermar 146
 
1852 jermar 147
    dtlb_tag_access_write(tag.value);
2141 jermar 148
 
1852 jermar 149
    data.value = 0;
150
    data.v = true;
151
    data.size = PAGESIZE_8K;
152
    data.pfn = fr.pfn;
153
    data.l = false;
154
    data.cp = t->c;
2009 jermar 155
#ifdef CONFIG_VIRT_IDX_DCACHE
1852 jermar 156
    data.cv = t->c;
2009 jermar 157
#endif /* CONFIG_VIRT_IDX_DCACHE */
1864 jermar 158
    data.p = t->k;      /* p like privileged */
1852 jermar 159
    data.w = ro ? false : t->w;
160
    data.g = t->g;
2141 jermar 161
 
1852 jermar 162
    dtlb_data_in_write(data.value);
1851 jermar 163
}
164
 
1891 jermar 165
/** Copy PTE to ITLB.
166
 *
3672 jermar 167
 * @param t     Page Table Entry to be copied.
168
 * @param index     Zero if lower 8K-subpage, one if higher 8K-subpage.
1891 jermar 169
 */
2141 jermar 170
void itlb_pte_copy(pte_t *t, index_t index)
1852 jermar 171
{
172
    tlb_tag_access_reg_t tag;
173
    tlb_data_t data;
174
    page_address_t pg;
175
    frame_address_t fr;
176
 
2141 jermar 177
    pg.address = t->page + (index << MMU_PAGE_WIDTH);
178
    fr.address = t->frame + (index << MMU_PAGE_WIDTH);
1852 jermar 179
 
180
    tag.value = 0;
181
    tag.context = t->as->asid;
182
    tag.vpn = pg.vpn;
183
 
184
    itlb_tag_access_write(tag.value);
185
 
186
    data.value = 0;
187
    data.v = true;
188
    data.size = PAGESIZE_8K;
189
    data.pfn = fr.pfn;
190
    data.l = false;
191
    data.cp = t->c;
1864 jermar 192
    data.p = t->k;      /* p like privileged */
1852 jermar 193
    data.w = false;
194
    data.g = t->g;
195
 
196
    itlb_data_in_write(data.value);
197
}
198
 
863 jermar 199
/** ITLB miss handler. */
2231 jermar 200
void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate)
863 jermar 201
{
1852 jermar 202
    uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
2141 jermar 203
    index_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE;
1852 jermar 204
    pte_t *t;
205
 
206
    page_table_lock(AS, true);
207
    t = page_mapping_find(AS, va);
208
    if (t && PTE_EXECUTABLE(t)) {
209
        /*
210
         * The mapping was found in the software page hash table.
211
         * Insert it into ITLB.
212
         */
213
        t->a = true;
2141 jermar 214
        itlb_pte_copy(t, index);
1891 jermar 215
#ifdef CONFIG_TSB
2141 jermar 216
        itsb_pte_copy(t, index);
1891 jermar 217
#endif
1852 jermar 218
        page_table_unlock(AS, true);
219
    } else {
220
        /*
2048 jermar 221
         * Forward the page fault to the address space page fault
222
         * handler.
1852 jermar 223
         */    
224
        page_table_unlock(AS, true);
225
        if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
2048 jermar 226
            do_fast_instruction_access_mmu_miss_fault(istate,
2462 jermar 227
                __func__);
1852 jermar 228
        }
229
    }
863 jermar 230
}
231
 
1851 jermar 232
/** DTLB miss handler.
233
 *
2048 jermar 234
 * Note that some faults (e.g. kernel faults) were already resolved by the
235
 * low-level, assembly language part of the fast_data_access_mmu_miss handler.
2231 jermar 236
 *
3672 jermar 237
 * @param tag       Content of the TLB Tag Access register as it existed
238
 *          when the trap happened. This is to prevent confusion
239
 *          created by clobbered Tag Access register during a nested
240
 *          DTLB miss.
241
 * @param istate    Interrupted state saved on the stack.
1851 jermar 242
 */
2231 jermar 243
void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate)
863 jermar 244
{
1851 jermar 245
    uintptr_t va;
2141 jermar 246
    index_t index;
1851 jermar 247
    pte_t *t;
883 jermar 248
 
2141 jermar 249
    va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);
250
    index = tag.vpn % MMU_PAGES_PER_PAGE;
1865 jermar 251
 
1851 jermar 252
    if (tag.context == ASID_KERNEL) {
253
        if (!tag.vpn) {
254
            /* NULL access in kernel */
2048 jermar 255
            do_fast_data_access_mmu_miss_fault(istate, tag,
2462 jermar 256
                __func__);
1851 jermar 257
        }
2048 jermar 258
        do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected "
2141 jermar 259
            "kernel page fault.");
1851 jermar 260
    }
873 jermar 261
 
1851 jermar 262
    page_table_lock(AS, true);
263
    t = page_mapping_find(AS, va);
264
    if (t) {
265
        /*
266
         * The mapping was found in the software page hash table.
267
         * Insert it into DTLB.
268
         */
1852 jermar 269
        t->a = true;
2141 jermar 270
        dtlb_pte_copy(t, index, true);
1891 jermar 271
#ifdef CONFIG_TSB
2141 jermar 272
        dtsb_pte_copy(t, index, true);
1891 jermar 273
#endif
1851 jermar 274
        page_table_unlock(AS, true);
275
    } else {
276
        /*
2141 jermar 277
         * Forward the page fault to the address space page fault
278
         * handler.
1851 jermar 279
         */    
280
        page_table_unlock(AS, true);
281
        if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
2048 jermar 282
            do_fast_data_access_mmu_miss_fault(istate, tag,
2462 jermar 283
                __func__);
1851 jermar 284
        }
877 jermar 285
    }
863 jermar 286
}
287
 
2231 jermar 288
/** DTLB protection fault handler.
289
 *
3672 jermar 290
 * @param tag       Content of the TLB Tag Access register as it existed
291
 *          when the trap happened. This is to prevent confusion
292
 *          created by clobbered Tag Access register during a nested
293
 *          DTLB miss.
294
 * @param istate    Interrupted state saved on the stack.
2231 jermar 295
 */
296
void fast_data_access_protection(tlb_tag_access_reg_t tag, istate_t *istate)
863 jermar 297
{
1859 jermar 298
    uintptr_t va;
2141 jermar 299
    index_t index;
1859 jermar 300
    pte_t *t;
301
 
2141 jermar 302
    va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);
303
    index = tag.vpn % MMU_PAGES_PER_PAGE;   /* 16K-page emulation */
1859 jermar 304
 
305
    page_table_lock(AS, true);
306
    t = page_mapping_find(AS, va);
307
    if (t && PTE_WRITABLE(t)) {
308
        /*
2048 jermar 309
         * The mapping was found in the software page hash table and is
310
         * writable. Demap the old mapping and insert an updated mapping
311
         * into DTLB.
1859 jermar 312
         */
313
        t->a = true;
314
        t->d = true;
2141 jermar 315
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY,
316
            va + index * MMU_PAGE_SIZE);
317
        dtlb_pte_copy(t, index, false);
1891 jermar 318
#ifdef CONFIG_TSB
2141 jermar 319
        dtsb_pte_copy(t, index, false);
1891 jermar 320
#endif
1859 jermar 321
        page_table_unlock(AS, true);
322
    } else {
323
        /*
2048 jermar 324
         * Forward the page fault to the address space page fault
325
         * handler.
1859 jermar 326
         */    
327
        page_table_unlock(AS, true);
328
        if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
2048 jermar 329
            do_fast_data_access_protection_fault(istate, tag,
2462 jermar 330
                __func__);
1859 jermar 331
        }
332
    }
863 jermar 333
}
334
 
3672 jermar 335
/** Print TLB entry (for debugging purposes).
336
 *
337
 * The diag field has been left out in order to make this function more generic
338
 * (there is no diag field in US3 architeture).
339
 *
340
 * @param i     TLB entry number
341
 * @param t     TLB entry tag
342
 * @param d     TLB entry data
343
 */
344
static void print_tlb_entry(int i, tlb_tag_read_reg_t t, tlb_data_t d)
345
{
346
    printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
347
        "ie=%d, soft2=%#x, pfn=%#x, soft=%#x, l=%d, "
348
        "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
349
        t.context, d.v, d.size, d.nfo, d.ie, d.soft2,
350
        d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
351
}
352
 
353
#if defined (US)
354
 
570 jermar 355
/** Print contents of both TLBs. */
356
void tlb_print(void)
357
{
358
    int i;
359
    tlb_data_t d;
360
    tlb_tag_read_reg_t t;
361
 
362
    printf("I-TLB contents:\n");
363
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
364
        d.value = itlb_data_access_read(i);
613 jermar 365
        t.value = itlb_tag_read_read(i);
3672 jermar 366
        print_tlb_entry(i, t, d);
570 jermar 367
    }
368
 
369
    printf("D-TLB contents:\n");
370
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
371
        d.value = dtlb_data_access_read(i);
613 jermar 372
        t.value = dtlb_tag_read_read(i);
3672 jermar 373
        print_tlb_entry(i, t, d);
570 jermar 374
    }
3672 jermar 375
}
570 jermar 376
 
3672 jermar 377
#elif defined (US3)
378
 
379
/** Print contents of all TLBs. */
380
void tlb_print(void)
381
{
382
    int i;
383
    tlb_data_t d;
384
    tlb_tag_read_reg_t t;
385
 
386
    printf("TLB_ISMALL contents:\n");
387
    for (i = 0; i < tlb_ismall_size(); i++) {
388
        d.value = dtlb_data_access_read(TLB_ISMALL, i);
389
        t.value = dtlb_tag_read_read(TLB_ISMALL, i);
390
        print_tlb_entry(i, t, d);
391
    }
392
 
393
    printf("TLB_IBIG contents:\n");
394
    for (i = 0; i < tlb_ibig_size(); i++) {
395
        d.value = dtlb_data_access_read(TLB_IBIG, i);
396
        t.value = dtlb_tag_read_read(TLB_IBIG, i);
397
        print_tlb_entry(i, t, d);
398
    }
399
 
400
    printf("TLB_DSMALL contents:\n");
401
    for (i = 0; i < tlb_dsmall_size(); i++) {
402
        d.value = dtlb_data_access_read(TLB_DSMALL, i);
403
        t.value = dtlb_tag_read_read(TLB_DSMALL, i);
404
        print_tlb_entry(i, t, d);
405
    }
406
 
407
    printf("TLB_DBIG_1 contents:\n");
408
    for (i = 0; i < tlb_dbig_size(); i++) {
409
        d.value = dtlb_data_access_read(TLB_DBIG_0, i);
410
        t.value = dtlb_tag_read_read(TLB_DBIG_0, i);
411
        print_tlb_entry(i, t, d);
412
    }
413
 
414
    printf("TLB_DBIG_2 contents:\n");
415
    for (i = 0; i < tlb_dbig_size(); i++) {
416
        d.value = dtlb_data_access_read(TLB_DBIG_1, i);
417
        t.value = dtlb_tag_read_read(TLB_DBIG_1, i);
418
        print_tlb_entry(i, t, d);
419
    }
570 jermar 420
}
617 jermar 421
 
3672 jermar 422
#endif
423
 
2141 jermar 424
void do_fast_instruction_access_mmu_miss_fault(istate_t *istate,
425
    const char *str)
1852 jermar 426
{
3790 svoboda 427
    fault_if_from_uspace(istate, "%s.", str);
1880 jermar 428
    dump_istate(istate);
3790 svoboda 429
    panic("%s.", str);
1852 jermar 430
}
431
 
2141 jermar 432
void do_fast_data_access_mmu_miss_fault(istate_t *istate,
433
    tlb_tag_access_reg_t tag, const char *str)
1851 jermar 434
{
435
    uintptr_t va;
436
 
2141 jermar 437
    va = tag.vpn << MMU_PAGE_WIDTH;
2231 jermar 438
    if (tag.context) {
3790 svoboda 439
        fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str, va,
2231 jermar 440
            tag.context);
441
    }
1880 jermar 442
    dump_istate(istate);
3790 svoboda 443
    printf("Faulting page: %p, ASID=%d.\n", va, tag.context);
444
    panic("%s.", str);
1851 jermar 445
}
446
 
2141 jermar 447
void do_fast_data_access_protection_fault(istate_t *istate,
448
    tlb_tag_access_reg_t tag, const char *str)
1859 jermar 449
{
450
    uintptr_t va;
451
 
2141 jermar 452
    va = tag.vpn << MMU_PAGE_WIDTH;
1859 jermar 453
 
2231 jermar 454
    if (tag.context) {
3790 svoboda 455
        fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str, va,
2231 jermar 456
            tag.context);
457
    }
1859 jermar 458
    printf("Faulting page: %p, ASID=%d\n", va, tag.context);
1880 jermar 459
    dump_istate(istate);
3790 svoboda 460
    panic("%s.", str);
1859 jermar 461
}
462
 
1946 jermar 463
void dump_sfsr_and_sfar(void)
464
{
465
    tlb_sfsr_reg_t sfsr;
466
    uintptr_t sfar;
467
 
468
    sfsr.value = dtlb_sfsr_read();
469
    sfar = dtlb_sfar_read();
470
 
3672 jermar 471
#if defined (US)
2048 jermar 472
    printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, "
2141 jermar 473
        "fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w,
474
        sfsr.ow, sfsr.fv);
3672 jermar 475
#elif defined (US3)
476
    printf("DTLB SFSR: nf=%d, asi=%#x, tm=%d, ft=%#x, e=%d, ct=%d, pr=%d, "
477
        "w=%d, ow=%d, fv=%d\n", sfsr.nf, sfsr.asi, sfsr.tm, sfsr.ft,
478
        sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv);
479
#endif
480
 
1946 jermar 481
    printf("DTLB SFAR: address=%p\n", sfar);
482
 
483
    dtlb_sfsr_write(0);
484
}
485
 
3672 jermar 486
#if defined (US3)
487
/** Invalidates given TLB entry if and only if it is non-locked or global.
488
 *
489
 * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1,
490
 *          TLB_ISMALL, TLB_IBIG).
491
 * @param entry     Entry index within the given TLB.
492
 */
493
static void tlb_invalidate_entry(int tlb, index_t entry)
494
{
495
    tlb_data_t d;
496
    tlb_tag_read_reg_t t;
497
 
498
    if (tlb == TLB_DSMALL || tlb == TLB_DBIG_0 || tlb == TLB_DBIG_1) {
499
        d.value = dtlb_data_access_read(tlb, entry);
500
        if (!d.l || d.g) {
501
            t.value = dtlb_tag_read_read(tlb, entry);
502
            d.v = false;
503
            dtlb_tag_access_write(t.value);
504
            dtlb_data_access_write(tlb, entry, d.value);
505
        }
506
    } else if (tlb == TLB_ISMALL || tlb == TLB_IBIG) {
507
        d.value = itlb_data_access_read(tlb, entry);
508
        if (!d.l || d.g) {
509
            t.value = itlb_tag_read_read(tlb, entry);
510
            d.v = false;
511
            itlb_tag_access_write(t.value);
512
            itlb_data_access_write(tlb, entry, d.value);
513
        }
514
    }
515
}
516
#endif
517
 
617 jermar 518
/** Invalidate all unlocked ITLB and DTLB entries. */
519
void tlb_invalidate_all(void)
520
{
521
    int i;
3672 jermar 522
 
2078 jermar 523
    /*
524
     * Walk all ITLB and DTLB entries and remove all unlocked mappings.
525
     *
526
     * The kernel doesn't use global mappings so any locked global mappings
3672 jermar 527
     * found must have been created by someone else. Their only purpose now
2078 jermar 528
     * is to collide with proper mappings. Invalidate immediately. It should
529
     * be safe to invalidate them as late as now.
530
     */
531
 
3672 jermar 532
#if defined (US)
533
    tlb_data_t d;
534
    tlb_tag_read_reg_t t;
535
 
617 jermar 536
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
537
        d.value = itlb_data_access_read(i);
2078 jermar 538
        if (!d.l || d.g) {
617 jermar 539
            t.value = itlb_tag_read_read(i);
540
            d.v = false;
541
            itlb_tag_access_write(t.value);
542
            itlb_data_access_write(i, d.value);
543
        }
544
    }
3672 jermar 545
 
617 jermar 546
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
547
        d.value = dtlb_data_access_read(i);
2078 jermar 548
        if (!d.l || d.g) {
617 jermar 549
            t.value = dtlb_tag_read_read(i);
550
            d.v = false;
551
            dtlb_tag_access_write(t.value);
552
            dtlb_data_access_write(i, d.value);
553
        }
554
    }
3672 jermar 555
 
556
#elif defined (US3)
557
 
558
    for (i = 0; i < tlb_ismall_size(); i++)
559
        tlb_invalidate_entry(TLB_ISMALL, i);
560
    for (i = 0; i < tlb_ibig_size(); i++)
561
        tlb_invalidate_entry(TLB_IBIG, i);
562
    for (i = 0; i < tlb_dsmall_size(); i++)
563
        tlb_invalidate_entry(TLB_DSMALL, i);
564
    for (i = 0; i < tlb_dbig_size(); i++)
565
        tlb_invalidate_entry(TLB_DBIG_0, i);
566
    for (i = 0; i < tlb_dbig_size(); i++)
567
        tlb_invalidate_entry(TLB_DBIG_1, i);
568
#endif
569
 
617 jermar 570
}
571
 
2048 jermar 572
/** Invalidate all ITLB and DTLB entries that belong to specified ASID
573
 * (Context).
617 jermar 574
 *
575
 * @param asid Address Space ID.
576
 */
577
void tlb_invalidate_asid(asid_t asid)
578
{
1865 jermar 579
    tlb_context_reg_t pc_save, ctx;
1860 jermar 580
 
1865 jermar 581
    /* switch to nucleus because we are mapped by the primary context */
582
    nucleus_enter();
583
 
584
    ctx.v = pc_save.v = mmu_primary_context_read();
1860 jermar 585
    ctx.context = asid;
1865 jermar 586
    mmu_primary_context_write(ctx.v);
1860 jermar 587
 
1865 jermar 588
    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
589
    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
1860 jermar 590
 
1865 jermar 591
    mmu_primary_context_write(pc_save.v);
592
 
593
    nucleus_leave();
617 jermar 594
}
595
 
2048 jermar 596
/** Invalidate all ITLB and DTLB entries for specified page range in specified
597
 * address space.
617 jermar 598
 *
3672 jermar 599
 * @param asid      Address Space ID.
600
 * @param page      First page which to sweep out from ITLB and DTLB.
601
 * @param cnt       Number of ITLB and DTLB entries to invalidate.
617 jermar 602
 */
1780 jermar 603
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
617 jermar 604
{
2745 decky 605
    unsigned int i;
1865 jermar 606
    tlb_context_reg_t pc_save, ctx;
727 jermar 607
 
1865 jermar 608
    /* switch to nucleus because we are mapped by the primary context */
609
    nucleus_enter();
610
 
611
    ctx.v = pc_save.v = mmu_primary_context_read();
1860 jermar 612
    ctx.context = asid;
1865 jermar 613
    mmu_primary_context_write(ctx.v);
1860 jermar 614
 
2141 jermar 615
    for (i = 0; i < cnt * MMU_PAGES_PER_PAGE; i++) {
2134 jermar 616
        itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY,
2141 jermar 617
            page + i * MMU_PAGE_SIZE);
2134 jermar 618
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY,
2141 jermar 619
            page + i * MMU_PAGE_SIZE);
727 jermar 620
    }
1860 jermar 621
 
1865 jermar 622
    mmu_primary_context_write(pc_save.v);
623
 
624
    nucleus_leave();
617 jermar 625
}
1702 cejka 626
 
1792 jermar 627
/** @}
1702 cejka 628
 */