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| Rev | Author | Line No. | Line |
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| 1882 | jermar | 1 | /* |
| 2 | * Copyright (C) 2006 Jakub Jermar |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 29 | /** @addtogroup sparc64 |
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| 30 | * @{ |
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| 31 | */ |
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| 32 | /** @file |
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| 33 | * |
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| 34 | */ |
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| 35 | |||
| 36 | #include <fpu_context.h> |
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| 37 | #include <arch/register.h> |
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| 38 | #include <arch/asm.h> |
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| 39 | |||
| 40 | void fpu_context_save(fpu_context_t *fctx) |
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| 41 | { |
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| 42 | fprs_reg_t fprs; |
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| 43 | |||
| 44 | fprs.value = fprs_read(); |
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| 45 | |||
| 46 | if (fprs.dl) { |
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| 47 | /* |
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| 48 | * The lower half of floating-point registers is dirty. |
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| 49 | * Spill it to memory. |
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| 50 | */ |
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| 51 | __asm__ volatile ( |
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| 52 | "std %%f0, %0\n" |
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| 53 | "std %%f2, %1\n" |
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| 54 | "std %%f4, %2\n" |
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| 55 | "std %%f6, %3\n" |
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| 56 | "std %%f8, %4\n" |
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| 57 | "std %%f10, %5\n" |
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| 58 | "std %%f12, %6\n" |
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| 59 | "std %%f14, %7\n" |
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| 60 | "std %%f16, %8\n" |
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| 61 | "std %%f18, %9\n" |
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| 62 | "std %%f20, %10\n" |
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| 63 | "std %%f22, %11\n" |
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| 64 | "std %%f24, %12\n" |
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| 65 | "std %%f26, %13\n" |
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| 66 | "std %%f28, %14\n" |
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| 67 | "std %%f30, %15\n" |
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| 68 | : "=m" (fctx->d[0]), "=m" (fctx->d[1]), "=m" (fctx->d[2]), "=m" (fctx->d[3]), |
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| 69 | "=m" (fctx->d[4]), "=m" (fctx->d[5]), "=m" (fctx->d[6]), "=m" (fctx->d[7]), |
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| 70 | "=m" (fctx->d[8]), "=m" (fctx->d[9]), "=m" (fctx->d[10]), "=m" (fctx->d[11]), |
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| 71 | "=m" (fctx->d[12]), "=m" (fctx->d[13]), "=m" (fctx->d[14]), "=m" (fctx->d[15]) |
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| 72 | ); |
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| 73 | fprs.dl = false; |
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| 74 | } |
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| 75 | |||
| 76 | if (fprs.du) { |
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| 77 | /* |
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| 78 | * The upper half of floating-point registers is dirty. |
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| 79 | * Spill it to memory. |
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| 80 | */ |
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| 81 | __asm__ volatile ( |
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| 82 | "std %%f32, %0\n" |
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| 83 | "std %%f34, %1\n" |
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| 84 | "std %%f36, %2\n" |
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| 85 | "std %%f38, %3\n" |
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| 86 | "std %%f40, %4\n" |
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| 87 | "std %%f42, %5\n" |
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| 88 | "std %%f44, %6\n" |
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| 89 | "std %%f46, %7\n" |
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| 90 | "std %%f48, %8\n" |
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| 91 | "std %%f50, %9\n" |
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| 92 | "std %%f52, %10\n" |
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| 93 | "std %%f54, %11\n" |
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| 94 | "std %%f56, %12\n" |
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| 95 | "std %%f58, %13\n" |
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| 96 | "std %%f60, %14\n" |
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| 97 | "std %%f62, %15\n" |
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| 98 | : "=m" (fctx->d[16]), "=m" (fctx->d[17]), "=m" (fctx->d[18]), "=m" (fctx->d[19]), |
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| 99 | "=m" (fctx->d[20]), "=m" (fctx->d[21]), "=m" (fctx->d[22]), "=m" (fctx->d[23]), |
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| 100 | "=m" (fctx->d[24]), "=m" (fctx->d[25]), "=m" (fctx->d[26]), "=m" (fctx->d[27]), |
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| 101 | "=m" (fctx->d[28]), "=m" (fctx->d[29]), "=m" (fctx->d[30]), "=m" (fctx->d[31]) |
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| 102 | ); |
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| 103 | fprs.du = false; |
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| 104 | } |
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| 105 | |||
| 106 | fprs_write(fprs.value); |
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| 107 | |||
| 108 | __asm__ volatile ("stx %%fsr, %0\n" : "=m" (fctx->fsr)); |
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| 109 | } |
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| 110 | |||
| 111 | void fpu_context_restore(fpu_context_t *fctx) |
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| 112 | { |
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| 113 | fprs_reg_t fprs; |
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| 114 | |||
| 115 | fprs.value = fprs_read(); |
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| 116 | |||
| 117 | __asm__ volatile ( |
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| 118 | "ldd %0, %%f0\n" |
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| 119 | "ldd %1, %%f2\n" |
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| 120 | "ldd %2, %%f4\n" |
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| 121 | "ldd %3, %%f6\n" |
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| 122 | "ldd %4, %%f8\n" |
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| 123 | "ldd %5, %%f10\n" |
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| 124 | "ldd %6, %%f12\n" |
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| 125 | "ldd %7, %%f14\n" |
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| 126 | "ldd %8, %%f16\n" |
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| 127 | "ldd %9, %%f18\n" |
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| 128 | "ldd %10, %%f20\n" |
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| 129 | "ldd %11, %%f22\n" |
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| 130 | "ldd %12, %%f24\n" |
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| 131 | "ldd %13, %%f26\n" |
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| 132 | "ldd %14, %%f28\n" |
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| 133 | "ldd %15, %%f30\n" |
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| 134 | : |
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| 135 | : "m" (fctx->d[0]), "m" (fctx->d[1]), "m" (fctx->d[2]), "m" (fctx->d[3]), |
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| 136 | "m" (fctx->d[4]), "m" (fctx->d[5]), "m" (fctx->d[6]), "m" (fctx->d[7]), |
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| 137 | "m" (fctx->d[8]), "m" (fctx->d[9]), "m" (fctx->d[10]), "m" (fctx->d[11]), |
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| 138 | "m" (fctx->d[12]), "m" (fctx->d[13]), "m" (fctx->d[14]), "m" (fctx->d[15]) |
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| 139 | ); |
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| 140 | |||
| 141 | /* |
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| 142 | * We need to split loading of the floating-point registers because |
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| 143 | * GCC (4.1.1) can't handle more than 30 operands in one asm statement. |
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| 144 | */ |
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| 145 | |||
| 146 | __asm__ volatile ( |
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| 147 | "ldd %0, %%f32\n" |
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| 148 | "ldd %1, %%f34\n" |
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| 149 | "ldd %2, %%f36\n" |
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| 150 | "ldd %3, %%f38\n" |
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| 151 | "ldd %4, %%f40\n" |
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| 152 | "ldd %5, %%f42\n" |
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| 153 | "ldd %6, %%f44\n" |
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| 154 | "ldd %7, %%f46\n" |
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| 155 | "ldd %8, %%f48\n" |
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| 156 | "ldd %9, %%f50\n" |
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| 157 | "ldd %10, %%f52\n" |
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| 158 | "ldd %11, %%f54\n" |
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| 159 | "ldd %12, %%f56\n" |
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| 160 | "ldd %13, %%f58\n" |
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| 161 | "ldd %14, %%f60\n" |
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| 162 | "ldd %15, %%f62\n" |
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| 163 | : |
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| 164 | : "m" (fctx->d[16]), "m" (fctx->d[17]), "m" (fctx->d[18]), "m" (fctx->d[19]), |
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| 165 | "m" (fctx->d[20]), "m" (fctx->d[21]), "m" (fctx->d[22]), "m" (fctx->d[23]), |
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| 166 | "m" (fctx->d[24]), "m" (fctx->d[25]), "m" (fctx->d[26]), "m" (fctx->d[27]), |
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| 167 | "m" (fctx->d[28]), "m" (fctx->d[29]), "m" (fctx->d[30]), "m" (fctx->d[31]) |
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| 168 | ); |
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| 169 | |||
| 170 | fprs.dl = fprs.du = false; |
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| 171 | fprs_write(fprs.value); |
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| 172 | |||
| 173 | __asm__ volatile ("ldx %0, %%fsr\n" : : "m" (fctx->fsr)); |
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| 174 | } |
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| 175 | |||
| 176 | void fpu_enable(void) |
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| 177 | { |
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| 178 | pstate_reg_t pstate; |
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| 179 | |||
| 180 | pstate.value = pstate_read(); |
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| 181 | pstate.pef = true; |
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| 182 | pstate_write(pstate.value); |
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| 183 | } |
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| 184 | |||
| 185 | void fpu_disable(void) |
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| 186 | { |
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| 187 | pstate_reg_t pstate; |
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| 188 | |||
| 189 | pstate.value = pstate_read(); |
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| 190 | pstate.pef = false; |
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| 191 | pstate_write(pstate.value); |
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| 192 | } |
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| 193 | |||
| 194 | void fpu_init(void) |
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| 195 | { |
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| 196 | fpu_enable(); |
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| 197 | } |
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| 198 | |||
| 199 | /** @} |
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| 200 | */ |