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| Rev | Author | Line No. | Line |
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| 1889 | jermar | 1 | /* |
| 2071 | jermar | 2 | * Copyright (c) 2006 Jakub Jermar |
| 1889 | jermar | 3 | * All rights reserved. |
| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 29 | /** @addtogroup sparc64mm |
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| 30 | * @{ |
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| 31 | */ |
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| 32 | /** @file |
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| 33 | */ |
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| 34 | |||
| 35 | #ifndef KERN_sparc64_TSB_H_ |
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| 36 | #define KERN_sparc64_TSB_H_ |
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| 37 | |||
| 38 | /* |
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| 39 | * ITSB abd DTSB will claim 64K of memory, which |
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| 40 | * is a nice number considered that it is one of |
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| 41 | * the page sizes supported by hardware, which, |
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| 42 | * again, is nice because TSBs need to be locked |
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| 43 | * in TLBs - only one TLB entry will do. |
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| 44 | */ |
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| 2048 | jermar | 45 | #define TSB_SIZE 2 /* when changing this, change |
| 46 | * as.c as well */ |
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| 47 | #define ITSB_ENTRY_COUNT (512 * (1 << TSB_SIZE)) |
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| 48 | #define DTSB_ENTRY_COUNT (512 * (1 << TSB_SIZE)) |
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| 1889 | jermar | 49 | |
| 1891 | jermar | 50 | #define TSB_TAG_TARGET_CONTEXT_SHIFT 48 |
| 51 | |||
| 52 | #ifndef __ASM__ |
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| 53 | |||
| 54 | #include <arch/mm/tte.h> |
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| 55 | #include <arch/mm/mmu.h> |
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| 56 | #include <arch/types.h> |
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| 57 | #include <typedefs.h> |
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| 58 | |||
| 59 | /** TSB Tag Target register. */ |
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| 60 | union tsb_tag_target { |
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| 61 | uint64_t value; |
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| 62 | struct { |
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| 63 | unsigned invalid : 1; /**< Invalidated by software. */ |
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| 64 | unsigned : 2; |
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| 65 | unsigned context : 13; /**< Software ASID. */ |
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| 66 | unsigned : 6; |
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| 67 | uint64_t va_tag : 42; /**< Virtual address bits <63:22>. */ |
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| 68 | } __attribute__ ((packed)); |
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| 69 | }; |
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| 70 | typedef union tsb_tag_target tsb_tag_target_t; |
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| 71 | |||
| 72 | /** TSB entry. */ |
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| 1889 | jermar | 73 | struct tsb_entry { |
| 1891 | jermar | 74 | tsb_tag_target_t tag; |
| 1889 | jermar | 75 | tte_data_t data; |
| 76 | } __attribute__ ((packed)); |
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| 77 | typedef struct tsb_entry tsb_entry_t; |
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| 78 | |||
| 1890 | jermar | 79 | /** TSB Base register. */ |
| 80 | union tsb_base_reg { |
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| 81 | uint64_t value; |
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| 82 | struct { |
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| 83 | uint64_t base : 51; /**< TSB base address, bits 63:13. */ |
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| 2048 | jermar | 84 | unsigned split : 1; /**< Split vs. common TSB for 8K and 64K |
| 85 | * pages. HelenOS uses only 8K pages |
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| 86 | * for user mappings, so we always set |
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| 87 | * this to 0. |
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| 88 | */ |
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| 1890 | jermar | 89 | unsigned : 9; |
| 2048 | jermar | 90 | unsigned size : 3; /**< TSB size. Number of entries is |
| 91 | * 512 * 2^size. */ |
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| 1890 | jermar | 92 | } __attribute__ ((packed)); |
| 93 | }; |
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| 94 | typedef union tsb_base_reg tsb_base_reg_t; |
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| 95 | |||
| 96 | /** Read ITSB Base register. |
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| 97 | * |
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| 98 | * @return Content of the ITSB Base register. |
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| 99 | */ |
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| 100 | static inline uint64_t itsb_base_read(void) |
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| 101 | { |
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| 102 | return asi_u64_read(ASI_IMMU, VA_IMMU_TSB_BASE); |
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| 103 | } |
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| 104 | |||
| 105 | /** Read DTSB Base register. |
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| 106 | * |
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| 107 | * @return Content of the DTSB Base register. |
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| 108 | */ |
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| 109 | static inline uint64_t dtsb_base_read(void) |
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| 110 | { |
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| 111 | return asi_u64_read(ASI_DMMU, VA_DMMU_TSB_BASE); |
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| 112 | } |
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| 113 | |||
| 114 | /** Write ITSB Base register. |
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| 115 | * |
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| 116 | * @param v New content of the ITSB Base register. |
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| 117 | */ |
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| 118 | static inline void itsb_base_write(uint64_t v) |
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| 119 | { |
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| 120 | asi_u64_write(ASI_IMMU, VA_IMMU_TSB_BASE, v); |
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| 121 | } |
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| 122 | |||
| 123 | /** Write DTSB Base register. |
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| 124 | * |
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| 125 | * @param v New content of the DTSB Base register. |
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| 126 | */ |
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| 127 | static inline void dtsb_base_write(uint64_t v) |
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| 128 | { |
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| 129 | asi_u64_write(ASI_DMMU, VA_DMMU_TSB_BASE, v); |
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| 130 | } |
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| 131 | |||
| 1889 | jermar | 132 | extern void tsb_invalidate(as_t *as, uintptr_t page, count_t pages); |
| 1891 | jermar | 133 | extern void itsb_pte_copy(pte_t *t); |
| 134 | extern void dtsb_pte_copy(pte_t *t, bool ro); |
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| 1889 | jermar | 135 | |
| 1891 | jermar | 136 | #endif /* !def __ASM__ */ |
| 137 | |||
| 1889 | jermar | 138 | #endif |
| 139 | |||
| 140 | /** @} |
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| 141 | */ |