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894 jermar 1 
/*
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 * Copyright (c) 2006 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup sparc64
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 * @{
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 */
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/** @file
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 */
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#ifndef KERN_sparc64_Z8530_H_
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#define KERN_sparc64_Z8530_H_
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#include <arch/types.h>
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#include <arch/drivers/kbd.h>
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#define Z8530_CHAN_A    4
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#define Z8530_CHAN_B    0
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#define WR0 0
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#define WR1 1
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#define WR2 2
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#define WR3 3
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#define WR4 4
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#define WR5 5
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#define WR6 6
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#define WR7 7
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#define WR8 8
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#define WR9 9
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#define WR10    10
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#define WR11    11
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#define WR12    12
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#define WR13    13
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#define WR14    14
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#define WR15    15
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#define RR0 0
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#define RR1 1
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#define RR2 2
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#define RR3 3
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#define RR8 8
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#define RR10    10
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#define RR12    12
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#define RR13    13
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#define RR14    14
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#define RR15    15
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/* Write Register 0 */
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#define WR0_TX_IP_RST   (0x5<<3)    /** Reset pending TX interrupt. */
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#define WR0_ERR_RST (0x6<<3)
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/* Write Register 1 */
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#define WR1_RID     (0x0<<3)    /** Receive Interrupts Disabled. */
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#define WR1_RIFCSC  (0x1<<3)    /** Receive Interrupt on First Character or Special Condition. */
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#define WR1_IARCSC  (0x2<<3)    /** Interrupt on All Receive Characters or Special Conditions. */
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#define WR1_RISC    (0x3<<3)    /** Receive Interrupt on Special Condition. */
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#define WR1_PISC    (0x1<<2)    /** Parity Is Special Condition. */
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/* Write Register 3 */
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#define WR3_RX_ENABLE   (0x1<<0)    /** Rx Enable. */
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#define WR3_RX8BITSCH   (0x3<<6)    /** 8-bits per character. */
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/* Write Register 9 */
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#define WR9_MIE     (0x1<<3)    /** Master Interrupt Enable. */
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/* Read Register 0 */
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#define RR0_RCA     (0x1<<0)    /** Receive Character Available. */
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/** Structure representing the z8530 device. */
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typedef struct {
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    devno_t devno;
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    volatile uint8_t *reg;      /** Memory mapped registers of the z8530. */
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} z8530_t;
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static inline void z8530_write(z8530_t *dev, index_t chan, uint8_t reg, uint8_t val)
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{
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    /*
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     * Registers 8-15 will automatically issue the Point High
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     * command as their bit 3 is 1.
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     */
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    dev->reg[WR0+chan] = reg;   /* select register */
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    dev->reg[WR0+chan] = val;   /* write value */
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}
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static inline void z8530_write_a(z8530_t *dev, uint8_t reg, uint8_t val)
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{
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    z8530_write(dev, Z8530_CHAN_A, reg, val);
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}
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static inline void z8530_write_b(z8530_t *dev, uint8_t reg, uint8_t val)
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{
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    z8530_write(dev, Z8530_CHAN_B, reg, val);
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}
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static inline uint8_t z8530_read(z8530_t *dev, index_t chan, uint8_t reg)
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{
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    /*
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     * Registers 8-15 will automatically issue the Point High
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     * command as their bit 3 is 1.
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     */
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    dev->reg[WR0+chan] = reg;   /* select register */
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    return dev->reg[WR0+chan];
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}
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static inline uint8_t z8530_read_a(z8530_t *dev, uint8_t reg)
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{
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    return z8530_read(dev, Z8530_CHAN_A, reg);
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}
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static inline uint8_t z8530_read_b(z8530_t *dev, uint8_t reg)
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{
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    return z8530_read(dev, Z8530_CHAN_B, reg);
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}
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#endif
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/** @}
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 */