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| Rev | Author | Line No. | Line |
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| 894 | jermar | 1 | /* |
| 2 | * Copyright (C) 2006 Jakub Jermar |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 1784 | jermar | 29 | /** @addtogroup sparc64 |
| 1702 | cejka | 30 | * @{ |
| 31 | */ |
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| 32 | /** @file |
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| 33 | */ |
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| 34 | |||
| 1841 | jermar | 35 | #ifndef KERN_sparc64_Z8530_H_ |
| 36 | #define KERN_sparc64_Z8530_H_ |
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| 894 | jermar | 37 | |
| 895 | jermar | 38 | #include <arch/types.h> |
| 1848 | jermar | 39 | #include <typedefs.h> |
| 1842 | jermar | 40 | #include <arch/drivers/kbd.h> |
| 895 | jermar | 41 | |
| 1848 | jermar | 42 | #define Z8530_CHAN_A 4 |
| 43 | #define Z8530_CHAN_B 0 |
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| 895 | jermar | 44 | |
| 1848 | jermar | 45 | #define WR0 0 |
| 46 | #define WR1 1 |
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| 47 | #define WR2 2 |
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| 48 | #define WR3 3 |
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| 49 | #define WR4 4 |
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| 50 | #define WR5 5 |
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| 51 | #define WR6 6 |
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| 52 | #define WR7 7 |
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| 53 | #define WR8 8 |
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| 54 | #define WR9 9 |
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| 55 | #define WR10 10 |
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| 56 | #define WR11 11 |
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| 57 | #define WR12 12 |
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| 58 | #define WR13 13 |
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| 59 | #define WR14 14 |
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| 60 | #define WR15 15 |
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| 1410 | jermar | 61 | |
| 1848 | jermar | 62 | #define RR0 0 |
| 63 | #define RR1 1 |
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| 64 | #define RR2 2 |
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| 65 | #define RR3 3 |
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| 66 | #define RR8 8 |
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| 67 | #define RR10 10 |
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| 68 | #define RR12 12 |
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| 69 | #define RR13 13 |
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| 70 | #define RR14 14 |
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| 71 | #define RR15 15 |
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| 72 | |||
| 1849 | jermar | 73 | /* Write Register 0 */ |
| 74 | #define WR0_ERR_RST (0x6<<3) |
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| 75 | |||
| 1848 | jermar | 76 | /* Write Register 1 */ |
| 77 | #define WR1_RID (0x0<<3) /** Receive Interrupts Disabled. */ |
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| 78 | #define WR1_RIFCSC (0x1<<3) /** Receive Interrupt on First Character or Special Condition. */ |
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| 79 | #define WR1_IARCSC (0x2<<3) /** Interrupt on All Receive Characters or Special Conditions. */ |
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| 80 | #define WR1_RISC (0x3<<3) /** Receive Interrupt on Special Condition. */ |
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| 81 | #define WR1_PISC (0x1<<2) /** Parity Is Special Condition. */ |
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| 82 | |||
| 83 | /* Write Register 3 */ |
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| 84 | #define WR3_RX_ENABLE (0x1<<0) /** Rx Enable. */ |
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| 85 | #define WR3_RX8BITSCH (0x3<<6) /** 8-bits per character. */ |
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| 86 | |||
| 87 | /* Write Register 9 */ |
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| 88 | #define WR9_MIE (0x1<<3) /** Master Interrupt Enable. */ |
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| 89 | |||
| 90 | /* Read Register 0 */ |
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| 91 | #define RR0_RCA (0x1<<0) /** Receive Character Available. */ |
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| 92 | |||
| 93 | static inline void z8530_write(index_t chan, uint8_t reg, uint8_t val) |
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| 895 | jermar | 94 | { |
| 1848 | jermar | 95 | /* |
| 96 | * Registers 8-15 will automatically issue the Point High |
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| 97 | * command as their bit 3 is 1. |
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| 98 | */ |
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| 99 | kbd_virt_address[WR0+chan] = reg; /* select register */ |
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| 100 | kbd_virt_address[WR0+chan] = val; /* write value */ |
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| 895 | jermar | 101 | } |
| 102 | |||
| 1848 | jermar | 103 | static inline void z8530_write_a(uint8_t reg, uint8_t val) |
| 895 | jermar | 104 | { |
| 1848 | jermar | 105 | z8530_write(Z8530_CHAN_A, reg, val); |
| 895 | jermar | 106 | } |
| 1848 | jermar | 107 | static inline void z8530_write_b(uint8_t reg, uint8_t val) |
| 108 | { |
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| 109 | z8530_write(Z8530_CHAN_B, reg, val); |
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| 110 | } |
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| 895 | jermar | 111 | |
| 1848 | jermar | 112 | static inline uint8_t z8530_read(index_t chan, uint8_t reg) |
| 895 | jermar | 113 | { |
| 1848 | jermar | 114 | /* |
| 115 | * Registers 8-15 will automatically issue the Point High |
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| 116 | * command as their bit 3 is 1. |
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| 117 | */ |
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| 118 | kbd_virt_address[WR0+chan] = reg; /* select register */ |
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| 119 | return kbd_virt_address[WR0+chan]; |
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| 895 | jermar | 120 | } |
| 121 | |||
| 1848 | jermar | 122 | static inline uint8_t z8530_read_a(uint8_t reg) |
| 895 | jermar | 123 | { |
| 1848 | jermar | 124 | return z8530_read(Z8530_CHAN_A, reg); |
| 895 | jermar | 125 | } |
| 1848 | jermar | 126 | static inline uint8_t z8530_read_b(uint8_t reg) |
| 127 | { |
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| 128 | return z8530_read(Z8530_CHAN_B, reg); |
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| 129 | } |
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| 895 | jermar | 130 | |
| 894 | jermar | 131 | #endif |
| 1702 | cejka | 132 | |
| 1784 | jermar | 133 | /** @} |
| 1702 | cejka | 134 | */ |