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156 decky 1
/*
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 * Copyright (c) 2005 Martin Decky
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup ppc32  
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 * @{
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 */
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/** @file
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 */
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#ifndef KERN_ppc32_BARRIER_H_
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#define KERN_ppc32_BARRIER_H_
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#define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
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#define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
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#define memory_barrier() asm volatile ("sync" ::: "memory")
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#define read_barrier() asm volatile ("sync" ::: "memory")
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#define write_barrier() asm volatile ("eieio" ::: "memory")
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/*
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 * The IMB sequence used here is valid for all possible cache models
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 * on uniprocessor. SMP might require a different sequence.
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 * See PowerPC Programming Environment for 32-Bit Microprocessors,
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 * chapter 5.1.5.2
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 */
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static inline void smc_coherence(void *addr)
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{
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    asm volatile (
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        "dcbst 0, %0\n"
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        "sync\n"
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        "icbi 0, %0\n"
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        "sync\n"
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        "isync\n"
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        :: "r" (addr)
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    );
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}
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#define COHERENCE_INVAL_MIN 4
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static inline void smc_coherence_block(void *addr, unsigned long len)
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{
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    unsigned long i;
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    for (i = 0; i < len; i += COHERENCE_INVAL_MIN) {
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        asm volatile ("dcbst 0, %0\n" :: "r" (addr + i));
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    }
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    asm volatile ("sync");
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    for (i = 0; i < len; i += COHERENCE_INVAL_MIN) {
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        asm volatile ("icbi 0, %0\n" :: "r" (addr + i));
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    }
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    asm volatile (
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        "sync\n"
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        "isync\n"
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    );
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}
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#endif
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/** @}
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 */