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/*
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 * Copyright (c) 2003-2004 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup mips32mm   
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 * @{
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 */
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/** @file
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 */
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#ifndef KERN_mips32_PAGE_H_
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#define KERN_mips32_PAGE_H_
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#include <arch/mm/frame.h>
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#define PAGE_WIDTH  FRAME_WIDTH
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#define PAGE_SIZE   FRAME_SIZE
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#define PAGE_COLOR_BITS 0           /* dummy */
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#ifndef __ASM__
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#   define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
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#   define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
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#else
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#   define KA2PA(x) ((x) - 0x80000000)
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#   define PA2KA(x) ((x) + 0x80000000)
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#endif
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#ifdef KERNEL
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/*
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 * Implementation of generic 4-level page table interface.
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 *
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 * Page table layout:
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 * - 32-bit virtual addresses
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 * - Offset is 14 bits => pages are 16K long
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 * - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore
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 *   4 bytes long
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 * - PTE's replace EntryLo v (valid) bit with p (present) bit
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 * - PTE's use only one bit to distinguish between cacheable and uncacheable
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 *   mappings
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 * - PTE's define soft_valid field to ensure there is at least one 1 bit even if
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 *   the p bit is cleared
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 * - PTE's make use of CP0 EntryLo's two-bit reserved field for bit W (writable)
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 *   and bit A (accessed)
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 * - PTL0 has 64 entries (6 bits)
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 * - PTL1 is not used
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 * - PTL2 is not used
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 * - PTL3 has 4096 entries (12 bits)
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 */
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/* Macros describing number of entries in each level. */
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#define PTL0_ENTRIES_ARCH   64
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#define PTL1_ENTRIES_ARCH   0
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#define PTL2_ENTRIES_ARCH   0
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#define PTL3_ENTRIES_ARCH   4096
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/* Macros describing size of page tables in each level. */
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#define PTL0_SIZE_ARCH      ONE_FRAME
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#define PTL1_SIZE_ARCH      0
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#define PTL2_SIZE_ARCH      0
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#define PTL3_SIZE_ARCH      ONE_FRAME
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/* Macros calculating entry indices for each level. */
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#define PTL0_INDEX_ARCH(vaddr)  ((vaddr) >> 26) 
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#define PTL1_INDEX_ARCH(vaddr)  0
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#define PTL2_INDEX_ARCH(vaddr)  0
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#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 14) & 0xfff)
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/* Set accessor for PTL0 address. */
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#define SET_PTL0_ADDRESS_ARCH(ptl0)
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/* Get PTE address accessors for each level. */
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#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
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    (((pte_t *) (ptl0))[(i)].pfn << 12)
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#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
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    (ptl1)
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#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
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    (ptl2)
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#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
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    (((pte_t *) (ptl3))[(i)].pfn << 12)
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/* Set PTE address accessors for each level. */
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#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
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    (((pte_t *) (ptl0))[(i)].pfn = (a) >> 12)
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#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
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#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
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#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
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    (((pte_t *) (ptl3))[(i)].pfn = (a) >> 12)
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/* Get PTE flags accessors for each level. */
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#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
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    get_pt_flags((pte_t *) (ptl0), (index_t) (i))
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#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
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    PAGE_PRESENT
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#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
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    PAGE_PRESENT
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#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
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    get_pt_flags((pte_t *) (ptl3), (index_t) (i))
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/* Set PTE flags accessors for each level. */
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#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
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    set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
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#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
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#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
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#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
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    set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
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/* Last-level info macros. */
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#define PTE_VALID_ARCH(pte)         (*((uint32_t *) (pte)) != 0)
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#define PTE_PRESENT_ARCH(pte)           ((pte)->p != 0)
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#define PTE_GET_FRAME_ARCH(pte)         ((pte)->pfn << 12)
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#define PTE_WRITABLE_ARCH(pte)          ((pte)->w != 0)
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#define PTE_EXECUTABLE_ARCH(pte)        1
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#ifndef __ASM__
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#include <mm/mm.h>
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#include <arch/exception.h>
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static inline int get_pt_flags(pte_t *pt, index_t i)
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{
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    pte_t *p = &pt[i];
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    return ((p->cacheable << PAGE_CACHEABLE_SHIFT) |
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        ((!p->p) << PAGE_PRESENT_SHIFT) |
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        (1 << PAGE_USER_SHIFT) |
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        (1 << PAGE_READ_SHIFT) |
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        ((p->w) << PAGE_WRITE_SHIFT) |
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        (1 << PAGE_EXEC_SHIFT) |
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        (p->g << PAGE_GLOBAL_SHIFT));
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}
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static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
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{
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    pte_t *p = &pt[i];
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    p->cacheable = (flags & PAGE_CACHEABLE) != 0;
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    p->p = !(flags & PAGE_NOT_PRESENT);
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    p->g = (flags & PAGE_GLOBAL) != 0;
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    p->w = (flags & PAGE_WRITE) != 0;
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    /*
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     * Ensure that valid entries have at least one bit set.
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     */
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    p->soft_valid = 1;
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}
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extern void page_arch_init(void);
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#endif /* __ASM__ */
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#endif /* KERNEL */
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#endif
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/** @}
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 */