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740 jermar 1
/*
2
 * Copyright (C) 2006 Jakub Jermar
3
 * All rights reserved.
4
 *
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
7
 * are met:
8
 *
9
 * - Redistributions of source code must retain the above copyright
10
 *   notice, this list of conditions and the following disclaimer.
11
 * - Redistributions in binary form must reproduce the above copyright
12
 *   notice, this list of conditions and the following disclaimer in the
13
 *   documentation and/or other materials provided with the distribution.
14
 * - The name of the author may not be used to endorse or promote products
15
 *   derived from this software without specific prior written permission.
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
28
 
29
/*
30
 * TLB management.
31
 */
32
 
33
#include <mm/tlb.h>
901 jermar 34
#include <mm/asid.h>
902 jermar 35
#include <mm/page.h>
36
#include <mm/as.h>
818 vana 37
#include <arch/mm/tlb.h>
901 jermar 38
#include <arch/mm/page.h>
1210 vana 39
#include <arch/mm/vhpt.h>
819 vana 40
#include <arch/barrier.h>
900 jermar 41
#include <arch/interrupt.h>
928 vana 42
#include <arch/pal/pal.h>
43
#include <arch/asm.h>
899 jermar 44
#include <typedefs.h>
900 jermar 45
#include <panic.h>
993 jermar 46
#include <print.h>
902 jermar 47
#include <arch.h>
1621 vana 48
#include <interrupt.h>
740 jermar 49
 
756 jermar 50
/** Invalidate all TLB entries. */
740 jermar 51
void tlb_invalidate_all(void)
52
{
993 jermar 53
        ipl_t ipl;
928 vana 54
        __address adr;
993 jermar 55
        __u32 count1, count2, stride1, stride2;
928 vana 56
 
57
        int i,j;
58
 
993 jermar 59
        adr = PAL_PTCE_INFO_BASE();
60
        count1 = PAL_PTCE_INFO_COUNT1();
61
        count2 = PAL_PTCE_INFO_COUNT2();
62
        stride1 = PAL_PTCE_INFO_STRIDE1();
63
        stride2 = PAL_PTCE_INFO_STRIDE2();
928 vana 64
 
993 jermar 65
        ipl = interrupts_disable();
928 vana 66
 
993 jermar 67
        for(i = 0; i < count1; i++) {
68
            for(j = 0; j < count2; j++) {
69
                __asm__ volatile (
70
                    "ptc.e %0 ;;"
928 vana 71
                    :
993 jermar 72
                    : "r" (adr)
928 vana 73
                );
993 jermar 74
                adr += stride2;
928 vana 75
            }
993 jermar 76
            adr += stride1;
928 vana 77
        }
78
 
993 jermar 79
        interrupts_restore(ipl);
928 vana 80
 
81
        srlz_d();
82
        srlz_i();
1210 vana 83
#ifdef CONFIG_VHPT
84
        vhpt_invalidate_all();
85
#endif  
740 jermar 86
}
87
 
88
/** Invalidate entries belonging to an address space.
89
 *
90
 * @param asid Address space identifier.
91
 */
92
void tlb_invalidate_asid(asid_t asid)
93
{
935 vana 94
    tlb_invalidate_all();
740 jermar 95
}
818 vana 96
 
935 vana 97
 
947 vana 98
void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
935 vana 99
{
944 vana 100
    region_register rr;
101
    bool restore_rr = false;
993 jermar 102
    int b = 0;
103
    int c = cnt;
944 vana 104
 
947 vana 105
    __address va;
993 jermar 106
    va = page;
947 vana 107
 
944 vana 108
    rr.word = rr_read(VA2VRN(va));
109
    if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) {
110
        /*
111
         * The selected region register does not contain required RID.
112
         * Save the old content of the register and replace the RID.
113
         */
114
        region_register rr0;
115
 
116
        rr0 = rr;
117
        rr0.map.rid = ASID2RID(asid, VA2VRN(va));
118
        rr_write(VA2VRN(va), rr0.word);
119
        srlz_d();
120
        srlz_i();
121
    }
122
 
993 jermar 123
    while(c >>= 1)
124
        b++;
125
    b >>= 1;
944 vana 126
    __u64 ps;
127
 
993 jermar 128
    switch (b) {
944 vana 129
        case 0: /*cnt 1-3*/
993 jermar 130
            ps = PAGE_WIDTH;
944 vana 131
            break;
132
        case 1: /*cnt 4-15*/
947 vana 133
            /*cnt=((cnt-1)/4)+1;*/
993 jermar 134
            ps = PAGE_WIDTH+2;
135
            va &= ~((1<<ps)-1);
944 vana 136
            break;
137
        case 2: /*cnt 16-63*/
947 vana 138
            /*cnt=((cnt-1)/16)+1;*/
993 jermar 139
            ps = PAGE_WIDTH+4;
140
            va &= ~((1<<ps)-1);
944 vana 141
            break;
142
        case 3: /*cnt 64-255*/
947 vana 143
            /*cnt=((cnt-1)/64)+1;*/
993 jermar 144
            ps = PAGE_WIDTH+6;
145
            va &= ~((1<<ps)-1);
944 vana 146
            break;
147
        case 4: /*cnt 256-1023*/
947 vana 148
            /*cnt=((cnt-1)/256)+1;*/
993 jermar 149
            ps = PAGE_WIDTH+8;
150
            va &= ~((1<<ps)-1);
944 vana 151
            break;
152
        case 5: /*cnt 1024-4095*/
947 vana 153
            /*cnt=((cnt-1)/1024)+1;*/
993 jermar 154
            ps = PAGE_WIDTH+10;
155
            va &= ~((1<<ps)-1);
944 vana 156
            break;
157
        case 6: /*cnt 4096-16383*/
947 vana 158
            /*cnt=((cnt-1)/4096)+1;*/
993 jermar 159
            ps = PAGE_WIDTH+12;
160
            va &= ~((1<<ps)-1);
944 vana 161
            break;
162
        case 7: /*cnt 16384-65535*/
163
        case 8: /*cnt 65536-(256K-1)*/
947 vana 164
            /*cnt=((cnt-1)/16384)+1;*/
993 jermar 165
            ps = PAGE_WIDTH+14;
166
            va &= ~((1<<ps)-1);
944 vana 167
            break;
168
        default:
947 vana 169
            /*cnt=((cnt-1)/(16384*16))+1;*/
944 vana 170
            ps=PAGE_WIDTH+18;
171
            va&=~((1<<ps)-1);
172
            break;
173
    }
947 vana 174
    /*cnt+=(page!=va);*/
993 jermar 175
    for(; va<(page+cnt*(PAGE_SIZE)); va += (1<<ps)) {
176
        __asm__ volatile (
947 vana 177
            "ptc.l %0,%1;;"
178
            :
993 jermar 179
            : "r" (va), "r" (ps<<2)
947 vana 180
        );
944 vana 181
    }
182
    srlz_d();
183
    srlz_i();
184
 
185
    if (restore_rr) {
186
        rr_write(VA2VRN(va), rr.word);
187
        srlz_d();
188
        srlz_i();
189
    }
935 vana 190
}
191
 
899 jermar 192
/** Insert data into data translation cache.
193
 *
194
 * @param va Virtual page address.
195
 * @param asid Address space identifier.
196
 * @param entry The rest of TLB entry as required by TLB insertion format.
197
 */
919 jermar 198
void dtc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry)
199
{
899 jermar 200
    tc_mapping_insert(va, asid, entry, true);
201
}
818 vana 202
 
899 jermar 203
/** Insert data into instruction translation cache.
204
 *
205
 * @param va Virtual page address.
206
 * @param asid Address space identifier.
207
 * @param entry The rest of TLB entry as required by TLB insertion format.
208
 */
919 jermar 209
void itc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry)
210
{
899 jermar 211
    tc_mapping_insert(va, asid, entry, false);
212
}
818 vana 213
 
899 jermar 214
/** Insert data into instruction or data translation cache.
215
 *
216
 * @param va Virtual page address.
217
 * @param asid Address space identifier.
218
 * @param entry The rest of TLB entry as required by TLB insertion format.
219
 * @param dtc If true, insert into data translation cache, use instruction translation cache otherwise.
220
 */
221
void tc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, bool dtc)
818 vana 222
{
223
    region_register rr;
899 jermar 224
    bool restore_rr = false;
818 vana 225
 
901 jermar 226
    rr.word = rr_read(VA2VRN(va));
227
    if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) {
899 jermar 228
        /*
229
         * The selected region register does not contain required RID.
230
         * Save the old content of the register and replace the RID.
231
         */
232
        region_register rr0;
818 vana 233
 
899 jermar 234
        rr0 = rr;
901 jermar 235
        rr0.map.rid = ASID2RID(asid, VA2VRN(va));
236
        rr_write(VA2VRN(va), rr0.word);
899 jermar 237
        srlz_d();
238
        srlz_i();
818 vana 239
    }
899 jermar 240
 
241
    __asm__ volatile (
242
        "mov r8=psr;;\n"
900 jermar 243
        "rsm %0;;\n"            /* PSR_IC_MASK */
899 jermar 244
        "srlz.d;;\n"
245
        "srlz.i;;\n"
246
        "mov cr.ifa=%1\n"       /* va */
247
        "mov cr.itir=%2;;\n"        /* entry.word[1] */
248
        "cmp.eq p6,p7 = %4,r0;;\n"  /* decide between itc and dtc */
249
        "(p6) itc.i %3;;\n"
250
        "(p7) itc.d %3;;\n"
251
        "mov psr.l=r8;;\n"
252
        "srlz.d;;\n"
253
        :
900 jermar 254
        : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (dtc)
255
        : "p6", "p7", "r8"
899 jermar 256
    );
257
 
258
    if (restore_rr) {
901 jermar 259
        rr_write(VA2VRN(va), rr.word);
819 vana 260
        srlz_d();
899 jermar 261
        srlz_i();
818 vana 262
    }
899 jermar 263
}
818 vana 264
 
899 jermar 265
/** Insert data into instruction translation register.
266
 *
267
 * @param va Virtual page address.
268
 * @param asid Address space identifier.
269
 * @param entry The rest of TLB entry as required by TLB insertion format.
270
 * @param tr Translation register.
271
 */
272
void itr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr)
273
{
274
    tr_mapping_insert(va, asid, entry, false, tr);
275
}
818 vana 276
 
899 jermar 277
/** Insert data into data translation register.
278
 *
279
 * @param va Virtual page address.
280
 * @param asid Address space identifier.
281
 * @param entry The rest of TLB entry as required by TLB insertion format.
282
 * @param tr Translation register.
283
 */
284
void dtr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr)
285
{
286
    tr_mapping_insert(va, asid, entry, true, tr);
818 vana 287
}
288
 
899 jermar 289
/** Insert data into instruction or data translation register.
290
 *
291
 * @param va Virtual page address.
292
 * @param asid Address space identifier.
293
 * @param entry The rest of TLB entry as required by TLB insertion format.
294
 * @param dtc If true, insert into data translation register, use instruction translation register otherwise.
295
 * @param tr Translation register.
296
 */
297
void tr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr)
818 vana 298
{
299
    region_register rr;
899 jermar 300
    bool restore_rr = false;
818 vana 301
 
901 jermar 302
    rr.word = rr_read(VA2VRN(va));
303
    if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) {
899 jermar 304
        /*
305
         * The selected region register does not contain required RID.
306
         * Save the old content of the register and replace the RID.
307
         */
308
        region_register rr0;
818 vana 309
 
899 jermar 310
        rr0 = rr;
901 jermar 311
        rr0.map.rid = ASID2RID(asid, VA2VRN(va));
312
        rr_write(VA2VRN(va), rr0.word);
899 jermar 313
        srlz_d();
314
        srlz_i();
315
    }
818 vana 316
 
899 jermar 317
    __asm__ volatile (
318
        "mov r8=psr;;\n"
900 jermar 319
        "rsm %0;;\n"            /* PSR_IC_MASK */
899 jermar 320
        "srlz.d;;\n"
321
        "srlz.i;;\n"
322
        "mov cr.ifa=%1\n"           /* va */         
323
        "mov cr.itir=%2;;\n"        /* entry.word[1] */
324
        "cmp.eq p6,p7=%5,r0;;\n"    /* decide between itr and dtr */
325
        "(p6) itr.i itr[%4]=%3;;\n"
326
        "(p7) itr.d dtr[%4]=%3;;\n"
327
        "mov psr.l=r8;;\n"
328
        "srlz.d;;\n"
329
        :
900 jermar 330
        : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (tr), "r" (dtr)
331
        : "p6", "p7", "r8"
899 jermar 332
    );
333
 
334
    if (restore_rr) {
901 jermar 335
        rr_write(VA2VRN(va), rr.word);
819 vana 336
        srlz_d();
899 jermar 337
        srlz_i();
818 vana 338
    }
899 jermar 339
}
818 vana 340
 
901 jermar 341
/** Insert data into DTLB.
342
 *
1675 jermar 343
 * @param page Virtual page address including VRN bits.
344
 * @param frame Physical frame address.
901 jermar 345
 * @param dtr If true, insert into data translation register, use data translation cache otherwise.
346
 * @param tr Translation register if dtr is true, ignored otherwise.
347
 */
902 jermar 348
void dtlb_kernel_mapping_insert(__address page, __address frame, bool dtr, index_t tr)
901 jermar 349
{
350
    tlb_entry_t entry;
351
 
352
    entry.word[0] = 0;
353
    entry.word[1] = 0;
354
 
355
    entry.p = true;         /* present */
356
    entry.ma = MA_WRITEBACK;
357
    entry.a = true;         /* already accessed */
358
    entry.d = true;         /* already dirty */
359
    entry.pl = PL_KERNEL;
360
    entry.ar = AR_READ | AR_WRITE;
361
    entry.ppn = frame >> PPN_SHIFT;
362
    entry.ps = PAGE_WIDTH;
363
 
364
    if (dtr)
365
        dtr_mapping_insert(page, ASID_KERNEL, entry, tr);
366
    else
367
        dtc_mapping_insert(page, ASID_KERNEL, entry);
368
}
369
 
1675 jermar 370
/** Purge kernel entries from DTR.
371
 *
372
 * Purge DTR entries used by the kernel.
373
 *
374
 * @param page Virtual page address including VRN bits.
375
 * @param width Width of the purge in bits.
376
 */
377
void dtr_purge(__address page, count_t width)
378
{
379
    __asm__ volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width<<2));
380
}
381
 
382
 
902 jermar 383
/** Copy content of PTE into data translation cache.
384
 *
385
 * @param t PTE.
386
 */
387
void dtc_pte_copy(pte_t *t)
388
{
389
    tlb_entry_t entry;
390
 
391
    entry.word[0] = 0;
392
    entry.word[1] = 0;
393
 
394
    entry.p = t->p;
395
    entry.ma = t->c ? MA_WRITEBACK : MA_UNCACHEABLE;
396
    entry.a = t->a;
397
    entry.d = t->d;
398
    entry.pl = t->k ? PL_KERNEL : PL_USER;
399
    entry.ar = t->w ? AR_WRITE : AR_READ;
400
    entry.ppn = t->frame >> PPN_SHIFT;
401
    entry.ps = PAGE_WIDTH;
402
 
403
    dtc_mapping_insert(t->page, t->as->asid, entry);
1210 vana 404
#ifdef CONFIG_VHPT
405
    vhpt_mapping_insert(t->page, t->as->asid, entry);
406
#endif  
902 jermar 407
}
408
 
409
/** Copy content of PTE into instruction translation cache.
410
 *
411
 * @param t PTE.
412
 */
413
void itc_pte_copy(pte_t *t)
414
{
415
    tlb_entry_t entry;
416
 
417
    entry.word[0] = 0;
418
    entry.word[1] = 0;
419
 
420
    ASSERT(t->x);
421
 
422
    entry.p = t->p;
423
    entry.ma = t->c ? MA_WRITEBACK : MA_UNCACHEABLE;
424
    entry.a = t->a;
425
    entry.pl = t->k ? PL_KERNEL : PL_USER;
426
    entry.ar = t->x ? (AR_EXECUTE | AR_READ) : AR_READ;
427
    entry.ppn = t->frame >> PPN_SHIFT;
428
    entry.ps = PAGE_WIDTH;
429
 
430
    itc_mapping_insert(t->page, t->as->asid, entry);
1210 vana 431
#ifdef CONFIG_VHPT
432
    vhpt_mapping_insert(t->page, t->as->asid, entry);
433
#endif  
902 jermar 434
}
435
 
436
/** Instruction TLB fault handler for faults with VHPT turned off.
437
 *
438
 * @param vector Interruption vector.
958 jermar 439
 * @param istate Structure with saved interruption state.
902 jermar 440
 */
958 jermar 441
void alternate_instruction_tlb_fault(__u64 vector, istate_t *istate)
899 jermar 442
{
902 jermar 443
    region_register rr;
1411 jermar 444
    rid_t rid;
902 jermar 445
    __address va;
446
    pte_t *t;
447
 
958 jermar 448
    va = istate->cr_ifa;    /* faulting address */
1411 jermar 449
    rr.word = rr_read(VA2VRN(va));
450
    rid = rr.map.rid;
451
 
1044 jermar 452
    page_table_lock(AS, true);
902 jermar 453
    t = page_mapping_find(AS, va);
454
    if (t) {
455
        /*
456
         * The mapping was found in software page hash table.
457
         * Insert it into data translation cache.
458
         */
459
        itc_pte_copy(t);
1044 jermar 460
        page_table_unlock(AS, true);
902 jermar 461
    } else {
462
        /*
463
         * Forward the page fault to address space page fault handler.
464
         */
1044 jermar 465
        page_table_unlock(AS, true);
1411 jermar 466
        if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
1621 vana 467
            fault_if_from_uspace(istate,"Page fault at %P",va);
1411 jermar 468
            panic("%s: va=%p, rid=%d, iip=%p\n", __FUNCTION__, va, rid, istate->cr_iip);
902 jermar 469
        }
470
    }
899 jermar 471
}
818 vana 472
 
902 jermar 473
/** Data TLB fault handler for faults with VHPT turned off.
901 jermar 474
 *
475
 * @param vector Interruption vector.
958 jermar 476
 * @param istate Structure with saved interruption state.
901 jermar 477
 */
958 jermar 478
void alternate_data_tlb_fault(__u64 vector, istate_t *istate)
899 jermar 479
{
901 jermar 480
    region_register rr;
481
    rid_t rid;
482
    __address va;
902 jermar 483
    pte_t *t;
901 jermar 484
 
958 jermar 485
    va = istate->cr_ifa;    /* faulting address */
901 jermar 486
    rr.word = rr_read(VA2VRN(va));
487
    rid = rr.map.rid;
488
    if (RID2ASID(rid) == ASID_KERNEL) {
489
        if (VA2VRN(va) == VRN_KERNEL) {
490
            /*
491
             * Provide KA2PA(identity) mapping for faulting piece of
492
             * kernel address space.
493
             */
902 jermar 494
            dtlb_kernel_mapping_insert(va, KA2PA(va), false, 0);
901 jermar 495
            return;
496
        }
497
    }
919 jermar 498
 
1044 jermar 499
    page_table_lock(AS, true);
902 jermar 500
    t = page_mapping_find(AS, va);
501
    if (t) {
502
        /*
503
         * The mapping was found in software page hash table.
504
         * Insert it into data translation cache.
505
         */
506
        dtc_pte_copy(t);
1044 jermar 507
        page_table_unlock(AS, true);
902 jermar 508
    } else {
509
        /*
510
         * Forward the page fault to address space page fault handler.
511
         */
1044 jermar 512
        page_table_unlock(AS, true);
1411 jermar 513
        if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
1621 vana 514
            fault_if_from_uspace(istate,"Page fault at %P",va);
1221 decky 515
            panic("%s: va=%p, rid=%d, iip=%p\n", __FUNCTION__, va, rid, istate->cr_iip);
902 jermar 516
        }
517
    }
818 vana 518
}
519
 
902 jermar 520
/** Data nested TLB fault handler.
521
 *
522
 * This fault should not occur.
523
 *
524
 * @param vector Interruption vector.
958 jermar 525
 * @param istate Structure with saved interruption state.
902 jermar 526
 */
958 jermar 527
void data_nested_tlb_fault(__u64 vector, istate_t *istate)
899 jermar 528
{
529
    panic("%s\n", __FUNCTION__);
530
}
818 vana 531
 
902 jermar 532
/** Data Dirty bit fault handler.
533
 *
534
 * @param vector Interruption vector.
958 jermar 535
 * @param istate Structure with saved interruption state.
902 jermar 536
 */
958 jermar 537
void data_dirty_bit_fault(__u64 vector, istate_t *istate)
819 vana 538
{
1411 jermar 539
    region_register rr;
540
    rid_t rid;
541
    __address va;
902 jermar 542
    pte_t *t;
1411 jermar 543
 
544
    va = istate->cr_ifa;    /* faulting address */
545
    rr.word = rr_read(VA2VRN(va));
546
    rid = rr.map.rid;
902 jermar 547
 
1044 jermar 548
    page_table_lock(AS, true);
1411 jermar 549
    t = page_mapping_find(AS, va);
902 jermar 550
    ASSERT(t && t->p);
1411 jermar 551
    if (t && t->p && t->w) {
902 jermar 552
        /*
553
         * Update the Dirty bit in page tables and reinsert
554
         * the mapping into DTC.
555
         */
556
        t->d = true;
557
        dtc_pte_copy(t);
1411 jermar 558
    } else {
559
        if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
1621 vana 560
            fault_if_from_uspace(istate,"Page fault at %P",va);
1411 jermar 561
            panic("%s: va=%p, rid=%d, iip=%p\n", __FUNCTION__, va, rid, istate->cr_iip);
562
            t->d = true;
563
            dtc_pte_copy(t);
564
        }
902 jermar 565
    }
1044 jermar 566
    page_table_unlock(AS, true);
899 jermar 567
}
819 vana 568
 
902 jermar 569
/** Instruction access bit fault handler.
570
 *
571
 * @param vector Interruption vector.
958 jermar 572
 * @param istate Structure with saved interruption state.
902 jermar 573
 */
958 jermar 574
void instruction_access_bit_fault(__u64 vector, istate_t *istate)
899 jermar 575
{
1411 jermar 576
    region_register rr;
577
    rid_t rid;
578
    __address va;
579
    pte_t *t;  
902 jermar 580
 
1411 jermar 581
    va = istate->cr_ifa;    /* faulting address */
582
    rr.word = rr_read(VA2VRN(va));
583
    rid = rr.map.rid;
584
 
1044 jermar 585
    page_table_lock(AS, true);
1411 jermar 586
    t = page_mapping_find(AS, va);
902 jermar 587
    ASSERT(t && t->p);
1411 jermar 588
    if (t && t->p && t->x) {
902 jermar 589
        /*
590
         * Update the Accessed bit in page tables and reinsert
591
         * the mapping into ITC.
592
         */
593
        t->a = true;
594
        itc_pte_copy(t);
1411 jermar 595
    } else {
596
        if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
1621 vana 597
            fault_if_from_uspace(istate,"Page fault at %P",va);
1411 jermar 598
            panic("%s: va=%p, rid=%d, iip=%p\n", __FUNCTION__, va, rid, istate->cr_iip);
599
            t->a = true;
600
            itc_pte_copy(t);
601
        }
902 jermar 602
    }
1044 jermar 603
    page_table_unlock(AS, true);
899 jermar 604
}
819 vana 605
 
902 jermar 606
/** Data access bit fault handler.
607
 *
608
 * @param vector Interruption vector.
958 jermar 609
 * @param istate Structure with saved interruption state.
902 jermar 610
 */
958 jermar 611
void data_access_bit_fault(__u64 vector, istate_t *istate)
899 jermar 612
{
1411 jermar 613
    region_register rr;
614
    rid_t rid;
615
    __address va;
902 jermar 616
    pte_t *t;
617
 
1411 jermar 618
    va = istate->cr_ifa;    /* faulting address */
619
    rr.word = rr_read(VA2VRN(va));
620
    rid = rr.map.rid;
621
 
1044 jermar 622
    page_table_lock(AS, true);
1411 jermar 623
    t = page_mapping_find(AS, va);
902 jermar 624
    ASSERT(t && t->p);
625
    if (t && t->p) {
626
        /*
627
         * Update the Accessed bit in page tables and reinsert
628
         * the mapping into DTC.
629
         */
630
        t->a = true;
631
        dtc_pte_copy(t);
1411 jermar 632
    } else {
633
        if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
1621 vana 634
            fault_if_from_uspace(istate,"Page fault at %P",va);
1411 jermar 635
            panic("%s: va=%p, rid=%d, iip=%p\n", __FUNCTION__, va, rid, istate->cr_iip);
636
            t->a = true;
637
            itc_pte_copy(t);
638
        }
902 jermar 639
    }
1044 jermar 640
    page_table_unlock(AS, true);
819 vana 641
}
642
 
902 jermar 643
/** Page not present fault handler.
644
 *
645
 * @param vector Interruption vector.
958 jermar 646
 * @param istate Structure with saved interruption state.
902 jermar 647
 */
958 jermar 648
void page_not_present(__u64 vector, istate_t *istate)
819 vana 649
{
902 jermar 650
    region_register rr;
1411 jermar 651
    rid_t rid;
902 jermar 652
    __address va;
653
    pte_t *t;
654
 
958 jermar 655
    va = istate->cr_ifa;    /* faulting address */
1411 jermar 656
    rr.word = rr_read(VA2VRN(va));
657
    rid = rr.map.rid;
658
 
1044 jermar 659
    page_table_lock(AS, true);
902 jermar 660
    t = page_mapping_find(AS, va);
661
    ASSERT(t);
662
 
663
    if (t->p) {
664
        /*
665
         * If the Present bit is set in page hash table, just copy it
666
         * and update ITC/DTC.
667
         */
668
        if (t->x)
669
            itc_pte_copy(t);
670
        else
671
            dtc_pte_copy(t);
1044 jermar 672
        page_table_unlock(AS, true);
902 jermar 673
    } else {
1044 jermar 674
        page_table_unlock(AS, true);
1411 jermar 675
        if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
1621 vana 676
            fault_if_from_uspace(istate,"Page fault at %P",va);
1411 jermar 677
            panic("%s: va=%p, rid=%d\n", __FUNCTION__, va, rid);
902 jermar 678
        }
679
    }
819 vana 680
}