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35 jermar 1
/*
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 * Copyright (C) 2005 - 2006 Jakub Jermar
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 * Copyright (C) 2006 Jakub Vana
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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#ifndef __ia64_PAGE_H__
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#define __ia64_PAGE_H__
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#include <arch/mm/frame.h>
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#define PAGE_SIZE   FRAME_SIZE
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#define PAGE_WIDTH  FRAME_WIDTH
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#ifdef KERNEL
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/** Bit width of the TLB-locked portion of kernel address space. */
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#define KERNEL_PAGE_WIDTH   28  /* 256M */
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#define SET_PTL0_ADDRESS_ARCH(x)    /**< To be removed as situation permits. */
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#define PPN_SHIFT           12
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#define VRN_SHIFT           61
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#define VRN_MASK            (7LL << VRN_SHIFT)
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#define VA2VRN(va)          ((va)>>VRN_SHIFT)
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#ifdef __ASM__
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#define VRN_KERNEL          7
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#else
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#define VRN_KERNEL          7LL
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#endif
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#define REGION_REGISTERS        8
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#define KA2PA(x)    ((__address) (x-(VRN_KERNEL<<VRN_SHIFT)))
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#define PA2KA(x)    ((__address) (x+(VRN_KERNEL<<VRN_SHIFT)))
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#define VHPT_WIDTH          20          /* 1M */
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#define VHPT_SIZE           (1 << VHPT_WIDTH)
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#define VHPT_BASE           0       /* Must be aligned to VHPT_SIZE */
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#define PTA_BASE_SHIFT          15
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/** Memory Attributes. */
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#define MA_WRITEBACK    0x0
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#define MA_UNCACHEABLE  0x4
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/** Privilege Levels. Only the most and the least privileged ones are ever used. */
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#define PL_KERNEL   0x0
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#define PL_USER     0x3
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/* Access Rigths. Only certain combinations are used by the kernel. */
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#define AR_READ     0x0
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#define AR_EXECUTE  0x1
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#define AR_WRITE    0x2
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#ifndef __ASM__
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#include <arch/mm/frame.h>
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#include <arch/barrier.h>
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#include <genarch/mm/page_ht.h>
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#include <arch/mm/asid.h>
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#include <arch/types.h>
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#include <typedefs.h>
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#include <debug.h>
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struct vhpt_tag_info {
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    unsigned long long tag : 63;
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    unsigned ti : 1;
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} __attribute__ ((packed));
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union vhpt_tag {
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    struct vhpt_tag_info tag_info;
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    unsigned tag_word;
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};
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struct vhpt_entry_present {
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    /* Word 0 */
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    unsigned p : 1;
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    unsigned : 1;
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    unsigned ma : 3;
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    unsigned a : 1;
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    unsigned d : 1;
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    unsigned pl : 2;
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    unsigned ar : 3;
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    unsigned long long ppn : 38;
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    unsigned : 2;
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    unsigned ed : 1;
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    unsigned ig1 : 11;
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    /* Word 1 */
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    unsigned : 2;
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    unsigned ps : 6;
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    unsigned key : 24;
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    unsigned : 32;
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    /* Word 2 */
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    union vhpt_tag tag;
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    /* Word 3 */                                                   
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    __u64 ig3 : 64;
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} __attribute__ ((packed));
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struct vhpt_entry_not_present {
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    /* Word 0 */
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    unsigned p : 1;
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    unsigned long long ig0 : 52;
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    unsigned ig1 : 11;
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    /* Word 1 */
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    unsigned : 2;
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    unsigned ps : 6;
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    unsigned long long ig2 : 56;
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    /* Word 2 */
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    union vhpt_tag tag;
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    /* Word 3 */                                                   
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    __u64 ig3 : 64;
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} __attribute__ ((packed));
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typedef union vhpt_entry {
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    struct vhpt_entry_present present;
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    struct vhpt_entry_not_present not_present;
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    __u64 word[4];
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} vhpt_entry_t;
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struct region_register_map {
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    unsigned ve : 1;
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    unsigned : 1;
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    unsigned ps : 6;
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    unsigned rid : 24;
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    unsigned : 32;
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} __attribute__ ((packed));
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typedef union region_register {
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    struct region_register_map map;
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    unsigned long long word;
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} region_register;
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struct pta_register_map {
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    unsigned ve : 1;
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    unsigned : 1;
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    unsigned size : 6;
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    unsigned vf : 1;
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    unsigned : 6;
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    unsigned long long base : 49;
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} __attribute__ ((packed));
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typedef union pta_register {
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    struct pta_register_map map;
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    __u64 word;
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} pta_register;
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/** Return Translation Hashed Entry Address.
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 *
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 * VRN bits are used to read RID (ASID) from one
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 * of the eight region registers registers.
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 *
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 * @param va Virtual address including VRN bits.
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 *
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 * @return Address of the head of VHPT collision chain.
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 */
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static inline __u64 thash(__u64 va)
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{
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    __u64 ret;
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    __asm__ volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));
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    return ret;
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}
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/** Return Translation Hashed Entry Tag.
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 *
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 * VRN bits are used to read RID (ASID) from one
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 * of the eight region registers.
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 *
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 * @param va Virtual address including VRN bits.
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 *
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 * @return The unique tag for VPN and RID in the collision chain returned by thash().
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 */
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static inline __u64 ttag(__u64 va)
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{
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    __u64 ret;
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    __asm__ volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));
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    return ret;
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}
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/** Read Region Register.
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 *
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 * @param i Region register index.
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 *
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 * @return Current contents of rr[i].
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 */
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static inline __u64 rr_read(index_t i)
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{
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    __u64 ret;
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    ASSERT(i < REGION_REGISTERS);
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    __asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT));
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    return ret;
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}
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/** Write Region Register.
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 *
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 * @param i Region register index.
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 * @param v Value to be written to rr[i].
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 */
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static inline void rr_write(index_t i, __u64 v)
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{
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    ASSERT(i < REGION_REGISTERS);
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    __asm__ volatile (
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        "mov rr[%0] = %1\n"
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        :
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        : "r" (i << VRN_SHIFT), "r" (v)
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    );
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}
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/** Read Page Table Register.
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 *
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 * @return Current value stored in PTA.
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 */
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static inline __u64 pta_read(void)
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{
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    __u64 ret;
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    __asm__ volatile ("mov %0 = cr.pta\n" : "=r" (ret));
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    return ret;
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}
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/** Write Page Table Register.
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 *
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 * @param v New value to be stored in PTA.
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 */
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static inline void pta_write(__u64 v)
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{
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    __asm__ volatile ("mov cr.pta = %0\n" : : "r" (v));
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}
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extern void page_arch_init(void);
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extern vhpt_entry_t *vhpt_hash(__address page, asid_t asid);
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extern bool vhpt_compare(__address page, asid_t asid, vhpt_entry_t *v);
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extern void vhpt_set_record(vhpt_entry_t *v, __address page, asid_t asid, __address frame, int flags);
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#endif /* __ASM__ */
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#endif /* KERNEL */
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#endif