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35 jermar 1
/*
2071 jermar 2
 * Copyright (c) 2005 - 2006 Jakub Jermar
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 * Copyright (c) 2006 Jakub Vana
35 jermar 4
 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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1780 jermar 30
/** @addtogroup ia64mm 
1702 cejka 31
 * @{
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 */
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/** @file
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 */
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1888 jermar 36
#ifndef KERN_ia64_PAGE_H_
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#define KERN_ia64_PAGE_H_
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967 palkovsky 39
#include <arch/mm/frame.h>
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35 jermar 41
#define PAGE_SIZE   FRAME_SIZE
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#define PAGE_WIDTH  FRAME_WIDTH
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967 palkovsky 44
#ifdef KERNEL
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901 jermar 46
/** Bit width of the TLB-locked portion of kernel address space. */
2007 jermar 47
#define KERNEL_PAGE_WIDTH       28  /* 256M */
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#define IO_PAGE_WIDTH           26  /* 64M */
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#define FW_PAGE_WIDTH           28  /* 256M */
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3635 vana 51
#define USPACE_IO_PAGE_WIDTH        12  /* 4K */
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3635 vana 53
 
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/** Staticly mapped IO spaces - offsets to 0xe...00 of virtual adresses
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becauce of "minimal virtual bits implemented is 51"
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it is possible to have here values up to 0x0007000000000000
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*/
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3578 vana 60
/* Firmware area (bellow 4GB in phys mem) */
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#define FW_OFFSET             0x00000000F0000000
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/* Legacy IO space */
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#define IO_OFFSET             0x0001000000000000
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/* Videoram - now mapped to 0 as VGA text mode vram on 0xb8000*/
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#define VIO_OFFSET            0x0002000000000000
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749 jermar 70
#define PPN_SHIFT           12
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748 jermar 72
#define VRN_SHIFT           61
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#define VRN_MASK            (7LL << VRN_SHIFT)
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#define VA2VRN(va)          ((va)>>VRN_SHIFT)
869 vana 75
 
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#ifdef __ASM__
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#define VRN_KERNEL          7
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#else
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#define VRN_KERNEL          7LL
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#endif
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747 jermar 82
#define REGION_REGISTERS        8
715 vana 83
 
1780 jermar 84
#define KA2PA(x)    ((uintptr_t) (x-(VRN_KERNEL<<VRN_SHIFT)))
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#define PA2KA(x)    ((uintptr_t) (x+(VRN_KERNEL<<VRN_SHIFT)))
869 vana 86
 
2007 jermar 87
#define VHPT_WIDTH          20  /* 1M */
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#define VHPT_SIZE           (1 << VHPT_WIDTH)
715 vana 89
 
751 jermar 90
#define PTA_BASE_SHIFT          15
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/** Memory Attributes. */
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#define MA_WRITEBACK    0x0
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#define MA_UNCACHEABLE  0x4
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/** Privilege Levels. Only the most and the least privileged ones are ever used. */
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#define PL_KERNEL   0x0
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#define PL_USER     0x3
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/* Access Rigths. Only certain combinations are used by the kernel. */
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#define AR_READ     0x0
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#define AR_EXECUTE  0x1
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#define AR_WRITE    0x2
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901 jermar 105
#ifndef __ASM__
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2089 decky 107
#include <arch/mm/as.h>
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#include <arch/mm/frame.h>
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#include <arch/interrupt.h>
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#include <arch/barrier.h>
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#include <arch/mm/asid.h>
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#include <arch/types.h>
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#include <debug.h>
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747 jermar 115
struct vhpt_tag_info {
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    unsigned long long tag : 63;
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    unsigned ti : 1;
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} __attribute__ ((packed));
710 vana 119
 
747 jermar 120
union vhpt_tag {
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    struct vhpt_tag_info tag_info;
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    unsigned tag_word;
710 vana 123
};
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747 jermar 125
struct vhpt_entry_present {
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    /* Word 0 */
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    unsigned p : 1;
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    unsigned : 1;
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    unsigned ma : 3;
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    unsigned a : 1;
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    unsigned d : 1;
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    unsigned pl : 2;
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    unsigned ar : 3;
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    unsigned long long ppn : 38;
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    unsigned : 2;
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    unsigned ed : 1;
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    unsigned ig1 : 11;
710 vana 138
 
139
    /* Word 1 */
747 jermar 140
    unsigned : 2;
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    unsigned ps : 6;
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    unsigned key : 24;
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    unsigned : 32;
710 vana 144
 
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    /* Word 2 */
747 jermar 146
    union vhpt_tag tag;
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710 vana 148
    /* Word 3 */                                                   
1780 jermar 149
    uint64_t ig3 : 64;
747 jermar 150
} __attribute__ ((packed));
710 vana 151
 
747 jermar 152
struct vhpt_entry_not_present {
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    /* Word 0 */
747 jermar 154
    unsigned p : 1;
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    unsigned long long ig0 : 52;
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    unsigned ig1 : 11;
710 vana 157
 
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    /* Word 1 */
747 jermar 159
    unsigned : 2;
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    unsigned ps : 6;
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    unsigned long long ig2 : 56;
710 vana 162
 
747 jermar 163
    /* Word 2 */
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    union vhpt_tag tag;
710 vana 165
 
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    /* Word 3 */                                                   
1780 jermar 167
    uint64_t ig3 : 64;
747 jermar 168
} __attribute__ ((packed));
710 vana 169
 
747 jermar 170
typedef union vhpt_entry {
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    struct vhpt_entry_present present;
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    struct vhpt_entry_not_present not_present;
1780 jermar 173
    uint64_t word[4];
792 jermar 174
} vhpt_entry_t;
710 vana 175
 
747 jermar 176
struct region_register_map {
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    unsigned ve : 1;
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    unsigned : 1;
179
    unsigned ps : 6;
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    unsigned rid : 24;
181
    unsigned : 32;
182
} __attribute__ ((packed));
684 jermar 183
 
747 jermar 184
typedef union region_register {
185
    struct region_register_map map;
186
    unsigned long long word;
187
} region_register;
715 vana 188
 
747 jermar 189
struct pta_register_map {
190
    unsigned ve : 1;
191
    unsigned : 1;
192
    unsigned size : 6;
193
    unsigned vf : 1;
194
    unsigned : 6;
195
    unsigned long long base : 49;
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} __attribute__ ((packed));
197
 
198
typedef union pta_register {
199
    struct pta_register_map map;
1780 jermar 200
    uint64_t word;
747 jermar 201
} pta_register;
202
 
203
/** Return Translation Hashed Entry Address.
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 *
205
 * VRN bits are used to read RID (ASID) from one
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 * of the eight region registers registers.
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 *
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 * @param va Virtual address including VRN bits.
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 *
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 * @return Address of the head of VHPT collision chain.
211
 */
1780 jermar 212
static inline uint64_t thash(uint64_t va)
715 vana 213
{
1780 jermar 214
    uint64_t ret;
715 vana 215
 
2082 decky 216
    asm volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));
715 vana 217
 
747 jermar 218
    return ret;
219
}
220
 
221
/** Return Translation Hashed Entry Tag.
222
 *
223
 * VRN bits are used to read RID (ASID) from one
224
 * of the eight region registers.
225
 *
226
 * @param va Virtual address including VRN bits.
227
 *
228
 * @return The unique tag for VPN and RID in the collision chain returned by thash().
229
 */
1780 jermar 230
static inline uint64_t ttag(uint64_t va)
715 vana 231
{
1780 jermar 232
    uint64_t ret;
715 vana 233
 
2082 decky 234
    asm volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));
747 jermar 235
 
236
    return ret;
237
}
238
 
239
/** Read Region Register.
240
 *
241
 * @param i Region register index.
242
 *
243
 * @return Current contents of rr[i].
244
 */
1780 jermar 245
static inline uint64_t rr_read(index_t i)
715 vana 246
{
1780 jermar 247
    uint64_t ret;
748 jermar 248
    ASSERT(i < REGION_REGISTERS);
2082 decky 249
    asm volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT));
747 jermar 250
    return ret;
251
}
715 vana 252
 
747 jermar 253
/** Write Region Register.
254
 *
255
 * @param i Region register index.
256
 * @param v Value to be written to rr[i].
257
 */
1780 jermar 258
static inline void rr_write(index_t i, uint64_t v)
715 vana 259
{
748 jermar 260
    ASSERT(i < REGION_REGISTERS);
2082 decky 261
    asm volatile (
901 jermar 262
        "mov rr[%0] = %1\n"
263
        :
264
        : "r" (i << VRN_SHIFT), "r" (v)
265
    );
747 jermar 266
}
267
 
268
/** Read Page Table Register.
269
 *
270
 * @return Current value stored in PTA.
271
 */
1780 jermar 272
static inline uint64_t pta_read(void)
747 jermar 273
{
1780 jermar 274
    uint64_t ret;
747 jermar 275
 
2082 decky 276
    asm volatile ("mov %0 = cr.pta\n" : "=r" (ret));
747 jermar 277
 
278
    return ret;
279
}
715 vana 280
 
747 jermar 281
/** Write Page Table Register.
282
 *
283
 * @param v New value to be stored in PTA.
284
 */
1780 jermar 285
static inline void pta_write(uint64_t v)
747 jermar 286
{
2082 decky 287
    asm volatile ("mov cr.pta = %0\n" : : "r" (v));
747 jermar 288
}
715 vana 289
 
747 jermar 290
extern void page_arch_init(void);
291
 
1780 jermar 292
extern vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid);
293
extern bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v);
294
extern void vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame, int flags);
792 jermar 295
 
967 palkovsky 296
#endif /* __ASM__ */
869 vana 297
 
967 palkovsky 298
#endif /* KERNEL */
299
 
869 vana 300
#endif
1702 cejka 301
 
1780 jermar 302
/** @}
1702 cejka 303
 */