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173 jermar 1
/*
2071 jermar 2
 * Copyright (c) 2005 Jakub Jermar
173 jermar 3
 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup ia64   
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 * @{
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 */
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/** @file
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 */
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#ifndef KERN_ia64_ASM_H_
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#define KERN_ia64_ASM_H_
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#include <config.h>
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#include <arch/types.h>
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#include <arch/register.h>
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/** Return base address of current stack
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 *
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 * Return the base address of the current stack.
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 * The stack is assumed to be STACK_SIZE long.
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 * The stack must start on page boundary.
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 */
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static inline uintptr_t get_stack_base(void)
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{
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    uint64_t v;
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    __asm__ volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
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    return v;
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}
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/** Return Processor State Register.
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 *
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 * @return PSR.
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 */
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static inline uint64_t psr_read(void)
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{
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    uint64_t v;
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    __asm__ volatile ("mov %0 = psr\n" : "=r" (v));
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    return v;
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}
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/** Read IVA (Interruption Vector Address).
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 *
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 * @return Return location of interruption vector table.
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 */
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static inline uint64_t iva_read(void)
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{
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    uint64_t v;
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    __asm__ volatile ("mov %0 = cr.iva\n" : "=r" (v));
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    return v;
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}
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/** Write IVA (Interruption Vector Address) register.
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 *
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 * @param v New location of interruption vector table.
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 */
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static inline void iva_write(uint64_t v)
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{
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    __asm__ volatile ("mov cr.iva = %0\n" : : "r" (v));
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}
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92
 
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/** Read IVR (External Interrupt Vector Register).
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 *
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 * @return Highest priority, pending, unmasked external interrupt vector.
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 */
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static inline uint64_t ivr_read(void)
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{
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    uint64_t v;
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    __asm__ volatile ("mov %0 = cr.ivr\n" : "=r" (v));
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    return v;
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}
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/** Write ITC (Interval Timer Counter) register.
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 *
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 * @param v New counter value.
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 */
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static inline void itc_write(uint64_t v)
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{
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    __asm__ volatile ("mov ar.itc = %0\n" : : "r" (v));
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}
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/** Read ITC (Interval Timer Counter) register.
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 *
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 * @return Current counter value.
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 */
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static inline uint64_t itc_read(void)
432 jermar 120
{
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    uint64_t v;
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    __asm__ volatile ("mov %0 = ar.itc\n" : "=r" (v));
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125
    return v;
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}
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/** Write ITM (Interval Timer Match) register.
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 *
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 * @param v New match value.
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 */
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static inline void itm_write(uint64_t v)
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{
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    __asm__ volatile ("mov cr.itm = %0\n" : : "r" (v));
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}
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1488 vana 137
/** Read ITM (Interval Timer Match) register.
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 *
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 * @return Match value.
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 */
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static inline uint64_t itm_read(void)
1488 vana 142
{
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    uint64_t v;
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145
    __asm__ volatile ("mov %0 = cr.itm\n" : "=r" (v));
146
 
147
    return v;
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}
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/** Read ITV (Interval Timer Vector) register.
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 *
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 * @return Current vector and mask bit.
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 */
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static inline uint64_t itv_read(void)
433 jermar 155
{
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    uint64_t v;
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158
    __asm__ volatile ("mov %0 = cr.itv\n" : "=r" (v));
159
 
160
    return v;
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}
162
 
432 jermar 163
/** Write ITV (Interval Timer Vector) register.
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 *
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 * @param v New vector and mask bit.
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 */
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static inline void itv_write(uint64_t v)
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{
169
    __asm__ volatile ("mov cr.itv = %0\n" : : "r" (v));
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}
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/** Write EOI (End Of Interrupt) register.
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 *
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 * @param v This value is ignored.
432 jermar 175
 */
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static inline void eoi_write(uint64_t v)
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{
178
    __asm__ volatile ("mov cr.eoi = %0\n" : : "r" (v));
179
}
180
 
181
/** Read TPR (Task Priority Register).
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 *
183
 * @return Current value of TPR.
184
 */
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static inline uint64_t tpr_read(void)
432 jermar 186
{
1780 jermar 187
    uint64_t v;
432 jermar 188
 
189
    __asm__ volatile ("mov %0 = cr.tpr\n"  : "=r" (v));
190
 
191
    return v;
192
}
193
 
194
/** Write TPR (Task Priority Register).
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 *
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 * @param v New value of TPR.
432 jermar 197
 */
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static inline void tpr_write(uint64_t v)
432 jermar 199
{
200
    __asm__ volatile ("mov cr.tpr = %0\n" : : "r" (v));
201
}
202
 
203
/** Disable interrupts.
204
 *
205
 * Disable interrupts and return previous
206
 * value of PSR.
207
 *
208
 * @return Old interrupt priority level.
209
 */
210
static ipl_t interrupts_disable(void)
211
{
1780 jermar 212
    uint64_t v;
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214
    __asm__ volatile (
215
        "mov %0 = psr\n"
216
        "rsm %1\n"
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        : "=r" (v)
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        : "i" (PSR_I_MASK)
219
    );
220
 
221
    return (ipl_t) v;
222
}
223
 
224
/** Enable interrupts.
225
 *
226
 * Enable interrupts and return previous
227
 * value of PSR.
228
 *
229
 * @return Old interrupt priority level.
230
 */
231
static ipl_t interrupts_enable(void)
232
{
1780 jermar 233
    uint64_t v;
432 jermar 234
 
235
    __asm__ volatile (
236
        "mov %0 = psr\n"
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        "ssm %1\n"
238
        ";;\n"
239
        "srlz.d\n"
240
        : "=r" (v)
241
        : "i" (PSR_I_MASK)
242
    );
243
 
244
    return (ipl_t) v;
245
}
246
 
247
/** Restore interrupt priority level.
248
 *
249
 * Restore PSR.
250
 *
251
 * @param ipl Saved interrupt priority level.
252
 */
253
static inline void interrupts_restore(ipl_t ipl)
254
{
472 jermar 255
    if (ipl & PSR_I_MASK)
256
        (void) interrupts_enable();
257
    else
258
        (void) interrupts_disable();
432 jermar 259
}
260
 
261
/** Return interrupt priority level.
262
 *
263
 * @return PSR.
264
 */
265
static inline ipl_t interrupts_read(void)
266
{
919 jermar 267
    return (ipl_t) psr_read();
432 jermar 268
}
269
 
746 jermar 270
/** Disable protection key checking. */
271
static inline void pk_disable(void)
272
{
273
    __asm__ volatile ("rsm %0\n" : : "i" (PSR_PK_MASK));
274
}
275
 
432 jermar 276
extern void cpu_halt(void);
277
extern void cpu_sleep(void);
1780 jermar 278
extern void asm_delay_loop(uint32_t t);
238 vana 279
 
1780 jermar 280
extern void switch_to_userspace(uintptr_t entry, uintptr_t sp, uintptr_t bsp, uintptr_t uspace_uarg, uint64_t ipsr, uint64_t rsc);
919 jermar 281
 
173 jermar 282
#endif
1702 cejka 283
 
1888 jermar 284
/** @}
1702 cejka 285
 */