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1 jermar 1
/*
2071 jermar 2
 * Copyright (c) 2001-2004 Jakub Jermar
1 jermar 3
 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup ia32   
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 * @{
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 */
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/** @file
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 */
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1 jermar 35
#include <arch/pm.h>
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#include <config.h>
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#include <arch/types.h>
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#include <typedefs.h>
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#include <arch/interrupt.h>
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#include <arch/asm.h>
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#include <arch/context.h>
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#include <panic.h>
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#include <arch/mm/page.h>
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#include <mm/slab.h>
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#include <memstr.h>
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#include <arch/boot/boot.h>
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#include <interrupt.h>
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/*
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 * Early ia32 configuration functions and data structures.
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 */
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/*
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 * We have no use for segmentation so we set up flat mode. In this
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 * mode, we use, for each privilege level, two segments spanning the
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 * whole memory. One is for code and one is for data.
1112 palkovsky 57
 *
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 * One is for GS register which holds pointer to the TLS thread
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 * structure in it's base.
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 */
1187 jermar 61
descriptor_t gdt[GDT_ITEMS] = {
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    /* NULL descriptor */
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    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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    /* KTEXT descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
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    /* KDATA descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
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    /* UTEXT descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
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    /* UDATA descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
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    /* TSS descriptor - set up will be completed later */
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    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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    /* TLS descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
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    /* VESA Init descriptor */
1292 vana 77
#ifdef CONFIG_FB
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    { 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
1292 vana 79
#endif  
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};
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static idescriptor_t idt[IDT_ITEMS];
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static tss_t tss;
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tss_t *tss_p = NULL;
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/* gdtr is changed by kmp before next CPU is initialized */
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ptr_16_32_t bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((uintptr_t) gdt) };
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ptr_16_32_t gdtr = { .limit = sizeof(gdt), .base = (uintptr_t) gdt };
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1780 jermar 92
void gdt_setbase(descriptor_t *d, uintptr_t base)
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{
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    d->base_0_15 = base & 0xffff;
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    d->base_16_23 = ((base) >> 16) & 0xff;
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    d->base_24_31 = ((base) >> 24) & 0xff;
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}
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void gdt_setlimit(descriptor_t *d, uint32_t limit)
1 jermar 100
{
125 jermar 101
    d->limit_0_15 = limit & 0xffff;
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    d->limit_16_19 = (limit >> 16) & 0xf;
1 jermar 103
}
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1780 jermar 105
void idt_setoffset(idescriptor_t *d, uintptr_t offset)
1 jermar 106
{
112 jermar 107
    /*
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     * Offset is a linear address.
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     */
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    d->offset_0_15 = offset & 0xffff;
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    d->offset_16_31 = offset >> 16;
1 jermar 112
}
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1187 jermar 114
void tss_initialize(tss_t *t)
1 jermar 115
{
1780 jermar 116
    memsetb((uintptr_t) t, sizeof(struct tss), 0);
1 jermar 117
}
118
 
119
/*
120
 * This function takes care of proper setup of IDT and IDTR.
121
 */
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void idt_init(void)
123
{
1187 jermar 124
    idescriptor_t *d;
1 jermar 125
    int i;
125 jermar 126
 
1 jermar 127
    for (i = 0; i < IDT_ITEMS; i++) {
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        d = &idt[i];
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        d->unused = 0;
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        d->selector = selector(KTEXT_DES);
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        d->access = AR_PRESENT | AR_INTERRUPT;  /* masking interrupt */
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        if (i == VECTOR_SYSCALL) {
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            /*
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             * The syscall interrupt gate must be calleable from userland.
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             */
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            d->access |= DPL_USER;
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        }
141
 
1956 decky 142
        idt_setoffset(d, ((uintptr_t) interrupt_handlers) + i * interrupt_handler_size);
1 jermar 143
    }
144
}
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146
 
144 vana 147
/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
141 vana 148
static void clean_IOPL_NT_flags(void)
149
{
2082 decky 150
    asm volatile (
1187 jermar 151
        "pushfl\n"
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        "pop %%eax\n"
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        "and $0xffff8fff, %%eax\n"
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        "push %%eax\n"
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        "popfl\n"
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        : : : "eax"
141 vana 157
    );
158
}
159
 
144 vana 160
/* Clean AM(18) flag in CR0 register */
143 vana 161
static void clean_AM_flag(void)
162
{
2082 decky 163
    asm volatile (
1187 jermar 164
        "mov %%cr0, %%eax\n"
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        "and $0xfffbffff, %%eax\n"
166
        "mov %%eax, %%cr0\n"
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        : : : "eax"
143 vana 168
    );
169
}
141 vana 170
 
1 jermar 171
void pm_init(void)
172
{
1187 jermar 173
    descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
174
    ptr_16_32_t idtr;
1 jermar 175
 
176
    /*
232 jermar 177
     * Update addresses in GDT and IDT to their virtual counterparts.
178
     */
271 decky 179
    idtr.limit = sizeof(idt);
1780 jermar 180
    idtr.base = (uintptr_t) idt;
1186 jermar 181
    gdtr_load(&gdtr);
182
    idtr_load(&idtr);
232 jermar 183
 
184
    /*
1 jermar 185
     * Each CPU has its private GDT and TSS.
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     * All CPUs share one IDT.
187
     */
188
 
189
    if (config.cpu_active == 1) {
190
        idt_init();
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        /*
192
         * NOTE: bootstrap CPU has statically allocated TSS, because
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         * the heap hasn't been initialized so far.
194
         */
195
        tss_p = &tss;
196
    }
197
    else {
1187 jermar 198
        tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
1 jermar 199
        if (!tss_p)
68 decky 200
            panic("could not allocate TSS\n");
1 jermar 201
    }
202
 
203
    tss_initialize(tss_p);
204
 
205
    gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
206
    gdt_p[TSS_DES].special = 1;
1251 jermar 207
    gdt_p[TSS_DES].granularity = 0;
1 jermar 208
 
1780 jermar 209
    gdt_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
1251 jermar 210
    gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
1 jermar 211
 
212
    /*
213
     * As of this moment, the current CPU has its own GDT pointing
214
     * to its own TSS. We just need to load the TR register.
215
     */
1186 jermar 216
    tr_load(selector(TSS_DES));
141 vana 217
 
1251 jermar 218
    clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels and clear NT flag. */
144 vana 219
    clean_AM_flag();          /* Disable alignment check */
1 jermar 220
}
1112 palkovsky 221
 
1780 jermar 222
void set_tls_desc(uintptr_t tls)
1112 palkovsky 223
{
1187 jermar 224
    ptr_16_32_t cpugdtr;
1188 jermar 225
    descriptor_t *gdt_p;
1112 palkovsky 226
 
1186 jermar 227
    gdtr_store(&cpugdtr);
1188 jermar 228
    gdt_p = (descriptor_t *) cpugdtr.base;
1112 palkovsky 229
    gdt_setbase(&gdt_p[TLS_DES], tls);
230
    /* Reload gdt register to update GS in CPU */
1186 jermar 231
    gdtr_load(&cpugdtr);
1112 palkovsky 232
}
1702 cejka 233
 
1888 jermar 234
/** @}
1702 cejka 235
 */