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1 jermar 1
/*
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 * Copyright (c) 2001-2004 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup ia32mm 
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 * @{
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 */
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/** @file
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 */
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#ifndef KERN_ia32_PAGE_H_
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#define KERN_ia32_PAGE_H_
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#include <arch/mm/frame.h>
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#define PAGE_WIDTH  FRAME_WIDTH
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#define PAGE_SIZE   FRAME_SIZE
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#define PAGE_COLOR_BITS 0           /* dummy */
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#ifdef KERNEL
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#ifndef __ASM__
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#   define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
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#   define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
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#else
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#   define KA2PA(x) ((x) - 0x80000000)
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#   define PA2KA(x) ((x) + 0x80000000)
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#endif
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/*
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 * Implementation of generic 4-level page table interface.
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 * IA-32 has 2-level page tables, so PTL1 and PTL2 are left out.
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 */
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/* Number of entries in each level. */
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#define PTL0_ENTRIES_ARCH   1024
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#define PTL1_ENTRIES_ARCH   0
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#define PTL2_ENTRIES_ARCH   0
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#define PTL3_ENTRIES_ARCH   1024
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/* Page table sizes for each level. */
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#define PTL0_SIZE_ARCH      ONE_FRAME
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#define PTL1_SIZE_ARCH      0
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#define PTL2_SIZE_ARCH      0
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#define PTL3_SIZE_ARCH      ONE_FRAME
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/* Macros calculating indices for each level. */
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#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 22) & 0x3ff)
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#define PTL1_INDEX_ARCH(vaddr)  0
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#define PTL2_INDEX_ARCH(vaddr)  0
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#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x3ff)
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/* Get PTE address accessors for each level. */
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#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
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    ((pte_t *) ((((pte_t *) (ptl0))[(i)].frame_address) << 12))
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#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
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    (ptl1)
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#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
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    (ptl2)
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#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
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    ((uintptr_t) ((((pte_t *) (ptl3))[(i)].frame_address) << 12))
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/* Set PTE address accessors for each level. */
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#define SET_PTL0_ADDRESS_ARCH(ptl0) \
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    (write_cr3((uintptr_t) (ptl0)))
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#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
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    (((pte_t *) (ptl0))[(i)].frame_address = (a) >> 12)
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#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
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#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
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#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
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    (((pte_t *) (ptl3))[(i)].frame_address = (a) >> 12)
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/* Get PTE flags accessors for each level. */
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#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
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    get_pt_flags((pte_t *) (ptl0), (index_t) (i))
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#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
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    PAGE_PRESENT
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#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
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    PAGE_PRESENT
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#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
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    get_pt_flags((pte_t *) (ptl3), (index_t) (i))
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/* Set PTE flags accessors for each level. */
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#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
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    set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
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#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
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#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
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#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
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    set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
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/* Macros for querying the last level entries. */
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#define PTE_VALID_ARCH(p) \
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    (*((uint32_t *) (p)) != 0)
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#define PTE_PRESENT_ARCH(p) \
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    ((p)->present != 0)
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#define PTE_GET_FRAME_ARCH(p) \
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    ((p)->frame_address << FRAME_WIDTH)
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#define PTE_WRITABLE_ARCH(p) \
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    ((p)->writeable != 0)
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#define PTE_EXECUTABLE_ARCH(p)          1
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#ifndef __ASM__
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#include <mm/mm.h>
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#include <arch/interrupt.h>
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/* Page fault error codes. */
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/** When bit on this position is 0, the page fault was caused by a not-present
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 * page.
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 */
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#define PFERR_CODE_P        (1 << 0)
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/** When bit on this position is 1, the page fault was caused by a write. */
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#define PFERR_CODE_RW       (1 << 1)
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/** When bit on this position is 1, the page fault was caused in user mode. */
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#define PFERR_CODE_US       (1 << 2)
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/** When bit on this position is 1, a reserved bit was set in page directory. */
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#define PFERR_CODE_RSVD     (1 << 3)    
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static inline int get_pt_flags(pte_t *pt, index_t i)
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{
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    pte_t *p = &pt[i];
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    return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT |
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        (!p->present) << PAGE_PRESENT_SHIFT |
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        p->uaccessible << PAGE_USER_SHIFT |
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        1 << PAGE_READ_SHIFT |
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        p->writeable << PAGE_WRITE_SHIFT |
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        1 << PAGE_EXEC_SHIFT |
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        p->global << PAGE_GLOBAL_SHIFT);
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}
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static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
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{
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    pte_t *p = &pt[i];
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    p->page_cache_disable = !(flags & PAGE_CACHEABLE);
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    p->present = !(flags & PAGE_NOT_PRESENT);
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    p->uaccessible = (flags & PAGE_USER) != 0;
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    p->writeable = (flags & PAGE_WRITE) != 0;
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    p->global = (flags & PAGE_GLOBAL) != 0;
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    /*
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     * Ensure that there is at least one bit set even if the present bit is
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     * cleared.
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     */
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    p->soft_valid = true;
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}
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extern void page_arch_init(void);
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extern void page_fault(int n, istate_t *istate);
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#endif /* __ASM__ */
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#endif /* KERNEL */
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#endif
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/** @}
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 */