WebSVN – HelenOS – Blame – /trunk/kernel/arch/arm32/src/mm/page_fault.c

Rev	Author	Line No.	Line
2464	jermar	1	/*
		2	* Copyright (c) 2007 Pavel Jancik, Michal Kebrt
		3	* All rights reserved.
		4	*
		5	* Redistribution and use in source and binary forms, with or without
		6	* modification, are permitted provided that the following conditions
		7	* are met:
		8	*
		9	* - Redistributions of source code must retain the above copyright
		10	* notice, this list of conditions and the following disclaimer.
		11	* - Redistributions in binary form must reproduce the above copyright
		12	* notice, this list of conditions and the following disclaimer in the
		13	* documentation and/or other materials provided with the distribution.
		14	* - The name of the author may not be used to endorse or promote products
		15	* derived from this software without specific prior written permission.
		16	*
		17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
		18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
		19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
		20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
		21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
		22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
		23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
		24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
		25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
		26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		27	*/
		28
		29	/** @addtogroup arm32mm
		30	* @{
		31	*/
		32	/** @file
		33	* @brief Page fault related functions.
		34	*/
		35	#include <panic.h>
		36	#include <arch/exception.h>
		37	#include <arch/debug/print.h>
		38	#include <arch/mm/page_fault.h>
		39	#include <mm/as.h>
		40	#include <genarch/mm/page_pt.h>
		41	#include <arch.h>
		42	#include <interrupt.h>
		43
		44	/** Returns value stored in fault status register.
		45	*
		46	* @return Value stored in CP15 fault status register (FSR).
		47	*/
		48	static inline fault_status_t read_fault_status_register(void)
		49	{
		50	fault_status_union_t fsu;
		51
		52	/* fault status is stored in CP15 register 5 */
		53	asm volatile (
		54	"mrc p15, 0, %0, c5, c0, 0"
		55	: "=r"(fsu.dummy)
		56	);
		57	return fsu.fs;
		58	}
		59
		60	/** Returns FAR (fault address register) content.
		61	*
		62	* @return FAR (fault address register) content (address that caused a page
		63	* fault)
		64	*/
		65	static inline uintptr_t read_fault_address_register(void)
		66	{
		67	uintptr_t ret;
		68
		69	/* fault adress is stored in CP15 register 6 */
		70	asm volatile (
		71	"mrc p15, 0, %0, c6, c0, 0"
		72	: "=r"(ret)
		73	);
		74	return ret;
		75	}
		76
		77	/** Decides whether the instruction is load/store or not.
		78	*
		79	* @param instr Instruction
		80	*
		81	* @return true when instruction is load/store, false otherwise
		82	*/
		83	static inline bool is_load_store_instruction(instruction_t instr)
		84	{
		85	/* load store immediate offset */
		86	if (instr.type == 0x2) {
		87	return true;
		88	}
		89
		90	/* load store register offset */
		91	if (instr.type == 0x3 && instr.bit4 == 0) {
		92	return true;
		93	}
		94
		95	/* load store multiple */
		96	if (instr.type == 0x4) {
		97	return true;
		98	}
		99
		100	/* oprocessor load/store */
		101	if (instr.type == 0x6) {
		102	return true;
		103	}
		104
		105	return false;
		106	}
		107
		108	/** Decides whether the instruction is swap or not.
		109	*
		110	* @param instr Instruction
		111	*
		112	* @return true when instruction is swap, false otherwise
		113	*/
		114	static inline bool is_swap_instruction(instruction_t instr)
		115	{
		116	/* swap, swapb instruction */
		117	if (instr.type == 0x0 &&
		118	(instr.opcode == 0x8 \|\| instr.opcode == 0xa) &&
		119	instr.access == 0x0 && instr.bits567 == 0x4 && instr.bit4 == 1) {
		120	return true;
		121	}
		122
		123	return false;
		124	}
		125
		126	/** Decides whether read or write into memory is requested.
		127	*
		128	* @param instr_addr Address of instruction which tries to access memory.
		129	* @param badvaddr Virtual address the instruction tries to access.
		130	*
		131	* @return Type of access into memory, PF_ACCESS_EXEC if no memory access is
		132	* requested.
		133	*/
		134	static pf_access_t get_memory_access_type(uint32_t instr_addr,
		135	uintptr_t badvaddr)
		136	{
		137	instruction_union_t instr_union;
		138	instr_union.pc = instr_addr;
		139
		140	instruction_t instr = *(instr_union.instr);
		141
		142	/* undefined instructions */
		143	if (instr.condition == 0xf) {
		144	panic("page_fault - instruction doesn't access memory "
		145	"(instr_code: %x, badvaddr:%x)", instr, badvaddr);
		146	return PF_ACCESS_EXEC;
		147	}
		148
		149	/* load store instructions */
		150	if (is_load_store_instruction(instr)) {
		151	if (instr.access == 1) {
		152	return PF_ACCESS_READ;
		153	} else {
		154	return PF_ACCESS_WRITE;
		155	}
		156	}
		157
		158	/* swap, swpb instruction */
		159	if (is_swap_instruction(instr)) {
		160	return PF_ACCESS_WRITE;
		161	}
		162
		163	panic("page_fault - instruction doesn't access memory "
		164	"(instr_code: %x, badvaddr:%x)", instr, badvaddr);
		165
		166	return PF_ACCESS_EXEC;
		167	}
		168
		169	/** Handles "data abort" exception (load or store at invalid address).
		170	*
		171	* @param exc_no Exception number.
		172	* @param istate CPU state when exception occured.
		173	*/
		174	void data_abort(int exc_no, istate_t *istate)
		175	{
		176	fault_status_t fsr = read_fault_status_register();
		177	uintptr_t badvaddr = read_fault_address_register();
		178
		179	pf_access_t access = get_memory_access_type(istate->pc, badvaddr);
		180
		181	int ret = as_page_fault(badvaddr, access, istate);
		182
		183	if (ret == AS_PF_FAULT) {
		184	print_istate(istate);
		185	dprintf("page fault - pc: %x, va: %x, status: %x(%x), "
		186	"access:%d\n", istate->pc, badvaddr, fsr.status, fsr,
		187	access);
		188
		189	fault_if_from_uspace(istate, "Page fault: %#x", badvaddr);
		190	panic("page fault\n");
		191	}
		192	}
		193
		194	/** Handles "prefetch abort" exception (instruction couldn't be executed).
		195	*
		196	* @param exc_no Exception number.
		197	* @param istate CPU state when exception occured.
		198	*/
		199	void prefetch_abort(int exc_no, istate_t *istate)
		200	{
		201	int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate);
		202
		203	if (ret == AS_PF_FAULT) {
		204	dprintf("prefetch_abort\n");
		205	print_istate(istate);
		206	panic("page fault - prefetch_abort at address: %x\n",
		207	istate->pc);
		208	}
		209	}
		210
		211	/** @}
		212	*/

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