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| Rev | Author | Line No. | Line |
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| 2162 | stepan | 1 | /* |
| 2 | * Copyright (c) 2007 Petr Stepan |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 29 | /** @addtogroup arm32 |
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| 30 | * @{ |
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| 31 | */ |
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| 32 | /** @file |
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| 33 | */ |
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| 34 | |||
| 35 | #include<arch/asm.h> |
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| 36 | #include<arch/regutils.h> |
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| 37 | |||
| 38 | |||
| 39 | /** Disable interrupts. |
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| 40 | * |
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| 41 | * @return Old interrupt priority level. |
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| 42 | */ |
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| 43 | ipl_t interrupts_disable(void) |
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| 44 | { |
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| 2177 | stepan | 45 | ipl_t ipl = current_status_reg_read(); |
| 2162 | stepan | 46 | |
| 2177 | stepan | 47 | current_status_reg_control_write(ipl & ~STATUS_REG_IE_ENABLED_BIT); |
| 2162 | stepan | 48 | |
| 49 | return ipl; |
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| 50 | } |
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| 51 | |||
| 52 | /** Enable interrupts. |
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| 53 | * |
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| 54 | * @return Old interrupt priority level. |
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| 55 | */ |
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| 56 | ipl_t interrupts_enable(void) |
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| 57 | { |
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| 2177 | stepan | 58 | ipl_t ipl = current_status_reg_read(); |
| 2162 | stepan | 59 | |
| 2177 | stepan | 60 | current_status_reg_control_write(ipl | STATUS_REG_IE_ENABLED_BIT); |
| 2162 | stepan | 61 | |
| 62 | return ipl; |
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| 63 | } |
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| 64 | |||
| 65 | /** Restore interrupt priority level. |
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| 66 | * |
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| 67 | * @param ipl Saved interrupt priority level. |
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| 68 | */ |
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| 69 | void interrupts_restore(ipl_t ipl) |
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| 70 | { |
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| 2177 | stepan | 71 | current_status_reg_control_write(current_status_reg_read() | |
| 72 | (ipl & STATUS_REG_IE_ENABLED_BIT)); |
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| 2162 | stepan | 73 | } |
| 74 | |||
| 75 | /** Read interrupt priority level. |
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| 76 | * |
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| 77 | * @return Current interrupt priority level. |
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| 78 | */ |
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| 79 | ipl_t interrupts_read(void) |
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| 80 | { |
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| 2177 | stepan | 81 | return current_status_reg_read(); |
| 2162 | stepan | 82 | } |
| 83 | |||
| 84 | /** @} |
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| 85 | */ |