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2128 jermar 1
/*
2465 jermar 2
 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt
2128 jermar 3
 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup arm32mm
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 * @{
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 */
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/** @file
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 *  @brief Paging related declarations.
2128 jermar 34
 */
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36
#ifndef KERN_arm32_PAGE_H_
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#define KERN_arm32_PAGE_H_
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#include <arch/mm/frame.h>
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#include <mm/mm.h>
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#include <arch/exception.h>
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43
#define PAGE_WIDTH  FRAME_WIDTH
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#define PAGE_SIZE   FRAME_SIZE
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#define PAGE_COLOR_BITS 0           /* dummy */
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48
#ifndef __ASM__
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#   define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
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#   define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
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#else
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#   define KA2PA(x) ((x) - 0x80000000)
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#   define PA2KA(x) ((x) + 0x80000000)
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#endif
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56
#ifdef KERNEL
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/* Number of entries in each level. */
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#define PTL0_ENTRIES_ARCH   (2 << 12)   /* 4096 */
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#define PTL1_ENTRIES_ARCH   0
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#define PTL2_ENTRIES_ARCH   0
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/* coarse page tables used (256 * 4 = 1KB per page) */
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#define PTL3_ENTRIES_ARCH   (2 << 8)    /* 256 */
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/* Page table sizes for each level. */
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#define PTL0_SIZE_ARCH      FOUR_FRAMES
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#define PTL1_SIZE_ARCH      0
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#define PTL2_SIZE_ARCH      0
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#define PTL3_SIZE_ARCH      ONE_FRAME
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2467 jermar 71
/* Macros calculating indices into page tables for each level. */
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#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 20) & 0xfff)
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#define PTL1_INDEX_ARCH(vaddr)  0
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#define PTL2_INDEX_ARCH(vaddr)  0
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#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x0ff)
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/* Get PTE address accessors for each level. */
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#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
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    ((pte_t *) ((((pte_level0_t *)(ptl0))[(i)]).coarse_table_addr << 10))
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#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
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    (ptl1)
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#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
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    (ptl2)
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#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
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    ((uintptr_t) ((((pte_level1_t *)(ptl3))[(i)]).frame_base_addr << 12))
2128 jermar 86
 
2467 jermar 87
/* Set PTE address accessors for each level. */
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#define SET_PTL0_ADDRESS_ARCH(ptl0) \
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    (set_ptl0_addr((pte_level0_t *) (ptl0)))
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#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
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    (((pte_level0_t *) (ptl0))[(i)].coarse_table_addr = (a) >> 10)
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#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
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#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
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#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
95
    (((pte_level1_t *) (ptl3))[(i)].frame_base_addr = (a) >> 12)
2128 jermar 96
 
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/* Get PTE flags accessors for each level. */
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#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
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    get_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i))
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#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
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    PAGE_PRESENT
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#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
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    PAGE_PRESENT
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#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
105
    get_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i))
2128 jermar 106
 
2467 jermar 107
/* Set PTE flags accessors for each level. */
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#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
109
    set_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i), (x))
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#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
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#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
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#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
113
    set_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i), (x))
2128 jermar 114
 
2467 jermar 115
/* Macros for querying the last-level PTE entries. */
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#define PTE_VALID_ARCH(pte) \
117
    (*((uint32_t *) (pte)) != 0)
118
#define PTE_PRESENT_ARCH(pte) \
119
    (((pte_level0_t *) (pte))->descriptor_type != 0)
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#define PTE_GET_FRAME_ARCH(pte) \
121
    (((pte_level1_t *) (pte))->frame_base_addr << FRAME_WIDTH)
122
#define PTE_WRITABLE_ARCH(pte) \
123
    (((pte_level1_t *) (pte))->access_permission_0 == \
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        PTE_AP_USER_RW_KERNEL_RW)
125
#define PTE_EXECUTABLE_ARCH(pte) \
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    1
127
 
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#ifndef __ASM__
129
 
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/** Level 0 page table entry. */
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typedef struct {
132
    /* 0b01 for coarse tables, see below for details */
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    unsigned descriptor_type : 2;
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    unsigned impl_specific : 3;
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    unsigned domain : 4;
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    unsigned should_be_zero : 1;
2128 jermar 137
 
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    /* Pointer to the coarse 2nd level page table (holding entries for small
139
     * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page
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     * tables that may hold even tiny pages (1KB) but they are bigger (4KB
141
     * per table in comparison with 1KB per the coarse table)
142
     */
2467 jermar 143
    unsigned coarse_table_addr : 22;
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} ATTRIBUTE_PACKED pte_level0_t;
145
 
146
/** Level 1 page table entry (small (4KB) pages used). */
147
typedef struct {
148
 
149
    /* 0b10 for small pages */
2467 jermar 150
    unsigned descriptor_type : 2;
151
    unsigned bufferable : 1;
152
    unsigned cacheable : 1;
2465 jermar 153
 
154
    /* access permissions for each of 4 subparts of a page
155
     * (for each 1KB when small pages used */
156
    unsigned access_permission_0 : 2;
157
    unsigned access_permission_1 : 2;
158
    unsigned access_permission_2 : 2;
159
    unsigned access_permission_3 : 2;
2467 jermar 160
    unsigned frame_base_addr : 20;
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} ATTRIBUTE_PACKED pte_level1_t;
162
 
163
 
164
/* Level 1 page tables access permissions */
165
 
166
/** User mode: no access, privileged mode: no access. */
167
#define PTE_AP_USER_NO_KERNEL_NO    0
168
 
169
/** User mode: no access, privileged mode: read/write. */
170
#define PTE_AP_USER_NO_KERNEL_RW    1
171
 
172
/** User mode: read only, privileged mode: read/write. */
173
#define PTE_AP_USER_RO_KERNEL_RW    2
174
 
175
/** User mode: read/write, privileged mode: read/write. */
176
#define PTE_AP_USER_RW_KERNEL_RW    3
177
 
178
 
179
/* pte_level0_t and pte_level1_t descriptor_type flags */
180
 
181
/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */
182
#define PTE_DESCRIPTOR_NOT_PRESENT  0
183
 
184
/** pte_level0_t coarse page table flag (used in descriptor_type). */
185
#define PTE_DESCRIPTOR_COARSE_TABLE 1
186
 
187
/** pte_level1_t small page table flag (used in descriptor type). */
188
#define PTE_DESCRIPTOR_SMALL_PAGE   2
189
 
190
 
191
/** Sets the address of level 0 page table.
192
 *
193
 * @param pt    Pointer to the page table to set.
194
 */  
2467 jermar 195
static inline void set_ptl0_addr(pte_level0_t *pt)
2128 jermar 196
{
2465 jermar 197
    asm volatile (
198
        "mcr p15, 0, %0, c2, c0, 0 \n"
199
        :
200
        : "r"(pt)
201
    );
2128 jermar 202
}
203
 
2465 jermar 204
 
205
/** Returns level 0 page table entry flags.
206
 *
207
 *  @param pt     Level 0 page table.
208
 *  @param i      Index of the entry to return.
209
 */
210
static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i)
2128 jermar 211
{
2465 jermar 212
    pte_level0_t *p = &pt[i];
213
    int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT);
214
 
215
    return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) |
216
        (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) |
217
        (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT);
2128 jermar 218
}
219
 
2465 jermar 220
/** Returns level 1 page table entry flags.
221
 *
222
 *  @param pt     Level 1 page table.
223
 *  @param i      Index of the entry to return.
224
 */
225
static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i)
226
{
227
    pte_level1_t *p = &pt[i];
228
 
229
    int dt = p->descriptor_type;
230
    int ap = p->access_permission_0;
231
 
232
    return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) |
233
        ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) |
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        ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT) |
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        ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT) |
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        ((ap != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT) |
237
        ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT) |
238
        ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT) |
239
        (1 << PAGE_EXEC_SHIFT) |
240
        (p->bufferable << PAGE_CACHEABLE);
241
}
242
 
243
 
244
/** Sets flags of level 0 page table entry.
245
 *
246
 *  @param pt     level 0 page table
247
 *  @param i      index of the entry to be changed
248
 *  @param flags  new flags
249
 */
250
static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags)
251
{
252
    pte_level0_t *p = &pt[i];
253
 
254
    if (flags & PAGE_NOT_PRESENT) {
255
        p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
256
        /*
257
         * Ensures that the entry will be recognized as valid when
258
         * PTE_VALID_ARCH applied.
259
         */
260
        p->should_be_zero = 1;
261
    } else {
262
        p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
263
        p->should_be_zero = 0;
264
    }
265
}
266
 
267
 
268
/** Sets flags of level 1 page table entry.
269
 *
270
 *  We use same access rights for the whole page. When page is not preset we
271
 *  store 1 in acess_rigts_3 so that at least one bit is 1 (to mark correct
272
 *  page entry, see #PAGE_VALID_ARCH).
273
 *
274
 *  @param pt     Level 1 page table.
275
 *  @param i      Index of the entry to be changed.
276
 *  @param flags  New flags.
277
 */  
278
static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags)
279
{
280
    pte_level1_t *p = &pt[i];
281
 
282
    if (flags & PAGE_NOT_PRESENT) {
283
        p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
284
        p->access_permission_3 = 1;
285
    } else {
286
        p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
287
        p->access_permission_3 = p->access_permission_0;
288
    }
289
 
290
    p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
291
 
292
    /* default access permission */
293
    p->access_permission_0 = p->access_permission_1 =
294
        p->access_permission_2 = p->access_permission_3 =
295
        PTE_AP_USER_NO_KERNEL_RW;
296
 
297
    if (flags & PAGE_USER)  {
298
        if (flags & PAGE_READ) {
299
            p->access_permission_0 = p->access_permission_1 =
300
                p->access_permission_2 = p->access_permission_3 =
301
                PTE_AP_USER_RO_KERNEL_RW;
302
        }
303
        if (flags & PAGE_WRITE) {
304
            p->access_permission_0 = p->access_permission_1 =
305
                p->access_permission_2 = p->access_permission_3 =
306
                PTE_AP_USER_RW_KERNEL_RW;
307
        }
308
    }
309
}
310
 
311
 
2128 jermar 312
extern void page_arch_init(void);
313
 
2465 jermar 314
 
2128 jermar 315
#endif /* __ASM__ */
316
 
317
#endif /* KERNEL */
318
 
319
#endif
320
 
321
/** @}
322
 */