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178 palkovsky 1
/*
2701 jermar 2
 * Copyright (c) 2008 Jakub Jermar
2071 jermar 3
 * Copyright (c) 2005-2006 Ondrej Palkovsky
178 palkovsky 4
 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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1888 jermar 30
/** @addtogroup amd64  
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 * @{
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 */
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/** @file
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 */
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2227 decky 36
#include <arch.h>
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#include <arch/pm.h>
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#include <arch/asm.h>
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#include <mm/as.h>
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#include <mm/frame.h>
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#include <memstr.h>
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#include <mm/slab.h>
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178 palkovsky 44
/*
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 * There is no segmentation in long mode so we set up flat mode. In this
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 * mode, we use, for each privilege level, two segments spanning the
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 * whole memory. One is for code and one is for data.
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 */
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1187 jermar 50
descriptor_t gdt[GDT_ITEMS] = {
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    /* NULL descriptor */
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    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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    /* KTEXT descriptor */
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    { .limit_0_15  = 0xffff,
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      .base_0_15   = 0,
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      .base_16_23  = 0,
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      .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
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      .limit_16_19 = 0xf,
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      .available   = 0,
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      .longmode    = 1,
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      .special     = 0,
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      .granularity = 1,
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      .base_24_31  = 0 },
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    /* KDATA descriptor */
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    { .limit_0_15  = 0xffff,
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      .base_0_15   = 0,
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      .base_16_23  = 0,
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      .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL,
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      .limit_16_19 = 0xf,
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      .available   = 0,
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      .longmode    = 0,
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      .special     = 0,
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      .granularity = 1,
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      .base_24_31  = 0 },
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    /* UDATA descriptor */
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    { .limit_0_15  = 0xffff,
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      .base_0_15   = 0,
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      .base_16_23  = 0,
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      .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER,
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      .limit_16_19 = 0xf,
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      .available   = 0,
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      .longmode    = 0,
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      .special     = 1,
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      .granularity = 1,
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      .base_24_31  = 0 },
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    /* UTEXT descriptor */
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    { .limit_0_15  = 0xffff,
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      .base_0_15   = 0,
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      .base_16_23  = 0,
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      .access      = AR_PRESENT | AR_CODE | DPL_USER,
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      .limit_16_19 = 0xf,
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      .available   = 0,
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      .longmode    = 1,
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      .special     = 0,
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      .granularity = 1,
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      .base_24_31  = 0 },
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    /* KTEXT 32-bit protected, for protected mode before long mode */
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    { .limit_0_15  = 0xffff,
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      .base_0_15   = 0,
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      .base_16_23  = 0,
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      .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
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      .limit_16_19 = 0xf,
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      .available   = 0,
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      .longmode    = 0,
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      .special     = 1,
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      .granularity = 1,
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      .base_24_31  = 0 },
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    /* TSS descriptor - set up will be completed later,
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     * on AMD64 it is 64-bit - 2 items in table */
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    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1289 vana 111
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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    /* VESA Init descriptor */
1292 vana 113
#ifdef CONFIG_FB    
2701 jermar 114
    { 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_CODE | DPL_KERNEL,
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      0xf, 0, 0, 0, 0, 0
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    }
1292 vana 117
#endif
178 palkovsky 118
};
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1187 jermar 120
idescriptor_t idt[IDT_ITEMS];
178 palkovsky 121
 
2701 jermar 122
ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base = (uint64_t) gdt };
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ptr_16_64_t idtr = {.limit = sizeof(idt), .base = (uint64_t) idt };
229 palkovsky 124
 
1187 jermar 125
static tss_t tss;
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tss_t *tss_p = NULL;
178 palkovsky 127
 
1780 jermar 128
void gdt_tss_setbase(descriptor_t *d, uintptr_t base)
206 palkovsky 129
{
1187 jermar 130
    tss_descriptor_t *td = (tss_descriptor_t *) d;
206 palkovsky 131
 
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    td->base_0_15 = base & 0xffff;
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    td->base_16_23 = ((base) >> 16) & 0xff;
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    td->base_24_31 = ((base) >> 24) & 0xff;
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    td->base_32_63 = ((base) >> 32);
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}
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1780 jermar 138
void gdt_tss_setlimit(descriptor_t *d, uint32_t limit)
206 palkovsky 139
{
4126 decky 140
    tss_descriptor_t *td = (tss_descriptor_t *) d;
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206 palkovsky 142
    td->limit_0_15 = limit & 0xffff;
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    td->limit_16_19 = (limit >> 16) & 0xf;
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}
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1780 jermar 146
void idt_setoffset(idescriptor_t *d, uintptr_t offset)
206 palkovsky 147
{
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    /*
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     * Offset is a linear address.
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     */
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    d->offset_0_15 = offset & 0xffff;
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    d->offset_16_31 = offset >> 16 & 0xffff;
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    d->offset_32_63 = offset >> 32;
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}
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1187 jermar 156
void tss_initialize(tss_t *t)
206 palkovsky 157
{
3104 svoboda 158
    memsetb(t, sizeof(tss_t), 0);
206 palkovsky 159
}
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161
/*
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 * This function takes care of proper setup of IDT and IDTR.
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 */
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void idt_init(void)
165
{
1187 jermar 166
    idescriptor_t *d;
206 palkovsky 167
    int i;
168
 
169
    for (i = 0; i < IDT_ITEMS; i++) {
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        d = &idt[i];
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172
        d->unused = 0;
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        d->selector = gdtselector(KTEXT_DES);
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175
        d->present = 1;
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        d->type = AR_INTERRUPT; /* masking interrupt */
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2701 jermar 178
        idt_setoffset(d, ((uintptr_t) interrupt_handlers) +
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            i * interrupt_handler_size);
206 palkovsky 180
    }
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}
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799 palkovsky 183
/** Initialize segmentation - code/data/idt tables
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 *
185
 */
206 palkovsky 186
void pm_init(void)
187
{
4126 decky 188
    descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
1187 jermar 189
    tss_descriptor_t *tss_desc;
4126 decky 190
 
206 palkovsky 191
    /*
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     * Each CPU has its private GDT and TSS.
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     * All CPUs share one IDT.
194
     */
4126 decky 195
 
206 palkovsky 196
    if (config.cpu_active == 1) {
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        idt_init();
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        /*
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         * NOTE: bootstrap CPU has statically allocated TSS, because
200
         * the heap hasn't been initialized so far.
201
         */
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        tss_p = &tss;
4126 decky 203
    } else {
1252 palkovsky 204
        /* We are going to use malloc, which may return
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         * non boot-mapped pointer, initialize the CR3 register
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         * ahead of page_init */
2106 jermar 207
        write_cr3((uintptr_t) AS_KERNEL->genarch.page_table);
4126 decky 208
 
209
        tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
206 palkovsky 210
        if (!tss_p)
3790 svoboda 211
            panic("Cannot allocate TSS.");
206 palkovsky 212
    }
4126 decky 213
 
206 palkovsky 214
    tss_initialize(tss_p);
4126 decky 215
 
1187 jermar 216
    tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
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    tss_desc->present = 1;
218
    tss_desc->type = AR_TSS;
219
    tss_desc->dpl = PL_KERNEL;
206 palkovsky 220
 
1780 jermar 221
    gdt_tss_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
1251 jermar 222
    gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
4126 decky 223
 
1186 jermar 224
    gdtr_load(&gdtr);
225
    idtr_load(&idtr);
206 palkovsky 226
    /*
227
     * As of this moment, the current CPU has its own GDT pointing
228
     * to its own TSS. We just need to load the TR register.
229
     */
1186 jermar 230
    tr_load(gdtselector(TSS_DES));
206 palkovsky 231
}
1702 cejka 232
 
1888 jermar 233
/** @}
1702 cejka 234
 */