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224 palkovsky 1
#
2071 jermar 2
# Copyright (c) 2005 Ondrej Palkovsky
224 palkovsky 3
# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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#
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# - Redistributions of source code must retain the above copyright
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#   notice, this list of conditions and the following disclaimer.
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# - Redistributions in binary form must reproduce the above copyright
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#   notice, this list of conditions and the following disclaimer in the
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#   documentation and/or other materials provided with the distribution.
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# - The name of the author may not be used to endorse or promote products
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#   derived from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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#define IREGISTER_SPACE 120
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#define IOFFSET_RAX 0x0
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#define IOFFSET_RBX 0x8
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#define IOFFSET_RCX 0x10
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#define IOFFSET_RDX 0x18
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#define IOFFSET_RSI 0x20
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#define IOFFSET_RDI 0x28
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#define IOFFSET_R8 0x30
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#define IOFFSET_R9 0x38
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#define IOFFSET_R10 0x40
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#define IOFFSET_R11 0x48
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#define IOFFSET_R12 0x50
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#define IOFFSET_R13 0x58
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#define IOFFSET_R14 0x60
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#define IOFFSET_R15 0x68
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#define IOFFSET_RBP 0x70
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#  Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word
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# and 1 means interrupt with error word
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#define ERROR_WORD_INTERRUPT_LIST 0x00027D00
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#include <arch/pm.h>
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#include <arch/mm/page.h>
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.text
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.global interrupt_handlers
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.global syscall_entry
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.global panic_printf
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panic_printf:
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	movq $halt, (%rsp)
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	jmp printf
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252 palkovsky 63
.global cpuid
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.global has_cpuid
2018 decky 65
.global get_cycle
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.global read_efer_flag
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.global set_efer_flag
1288 jermar 68
.global memcpy
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.global memcpy_from_uspace
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.global memcpy_to_uspace
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.global memcpy_from_uspace_failover_address
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.global memcpy_to_uspace_failover_address
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#define MEMCPY_DST	%rdi
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#define MEMCPY_SRC	%rsi
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#define MEMCPY_SIZE	%rdx
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/**
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 * Copy memory from/to userspace.
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 *
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 * This is almost conventional memcpy().
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 * The difference is that there is a failover part
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 * to where control is returned from a page fault if
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 * the page fault occurs during copy_from_uspace()
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 * or copy_to_uspace().
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 *
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 * @param MEMCPY_DST	Destination address.
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 * @param MEMCPY_SRC	Source address.
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 * @param MEMCPY_SIZE	Number of bytes to copy.
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 *
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 * @retrun MEMCPY_SRC on success, 0 on failure.
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 */
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memcpy:
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memcpy_from_uspace:
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memcpy_to_uspace:
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	movq MEMCPY_SRC, %rax
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	movq MEMCPY_SIZE, %rcx
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	shrq $3, %rcx			/* size / 8 */
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1288 jermar 101
	rep movsq			/* copy as much as possible word by word */
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	movq MEMCPY_SIZE, %rcx
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	andq $7, %rcx			/* size % 8 */
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	jz 0f
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	rep movsb			/* copy the rest byte by byte */
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0:
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	ret				/* return MEMCPY_SRC, success */
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memcpy_from_uspace_failover_address:
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memcpy_to_uspace_failover_address:
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	xorq %rax, %rax			/* return 0, failure */
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	ret
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242 palkovsky 117
## Determine CPUID support
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#
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# Return 0 in EAX if CPUID is not support, 1 if supported.
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#
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has_cpuid:
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	pushfq			# store flags
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	popq %rax		# read flags
348 jermar 124
	movq %rax,%rdx		# copy flags
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	btcl $21,%edx		# swap the ID bit
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	pushq %rdx
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	popfq			# propagate the change into flags
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	pushfq
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	popq %rdx		# read flags	
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	andl $(1<<21),%eax	# interested only in ID bit
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	andl $(1<<21),%edx
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	xorl %edx,%eax		# 0 if not supported, 1 if supported
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	ret
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cpuid:
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	movq %rbx, %r10  # we have to preserve rbx across function calls
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	movl %edi,%eax	# load the command into %eax
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	cpuid	
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	movl %eax,0(%rsi)
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	movl %ebx,4(%rsi)
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	movl %ecx,8(%rsi)
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	movl %edx,12(%rsi)
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	movq %r10, %rbx
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	ret
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2018 decky 149
get_cycle:
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	xorq %rax,%rax
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	rdtsc
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	ret
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set_efer_flag:
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	movq $0xc0000080, %rcx
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	rdmsr
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	btsl %edi, %eax
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	wrmsr
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	ret
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251 palkovsky 161
read_efer_flag:	
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	movq $0xc0000080, %rcx
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	rdmsr
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	ret 		
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224 palkovsky 166
# Push all general purpose registers on stack except %rbp, %rsp
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.macro save_all_gpr
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	movq %rax, IOFFSET_RAX(%rsp)
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	movq %rcx, IOFFSET_RCX(%rsp)
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	movq %rdx, IOFFSET_RDX(%rsp)
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	movq %rsi, IOFFSET_RSI(%rsp)
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	movq %rdi, IOFFSET_RDI(%rsp)
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	movq %r8, IOFFSET_R8(%rsp)
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	movq %r9, IOFFSET_R9(%rsp)
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	movq %r10, IOFFSET_R10(%rsp)
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	movq %r11, IOFFSET_R11(%rsp)
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#ifdef CONFIG_DEBUG_ALLREGS	
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	movq %rbx, IOFFSET_RBX(%rsp)
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	movq %rbp, IOFFSET_RBP(%rsp)
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	movq %r12, IOFFSET_R12(%rsp)
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	movq %r13, IOFFSET_R13(%rsp)
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	movq %r14, IOFFSET_R14(%rsp)
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	movq %r15, IOFFSET_R15(%rsp)
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#endif
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.endm
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.macro restore_all_gpr
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	movq IOFFSET_RAX(%rsp), %rax
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	movq IOFFSET_RCX(%rsp), %rcx
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	movq IOFFSET_RDX(%rsp), %rdx
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	movq IOFFSET_RSI(%rsp), %rsi
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	movq IOFFSET_RDI(%rsp), %rdi
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	movq IOFFSET_R8(%rsp), %r8
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	movq IOFFSET_R9(%rsp), %r9
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	movq IOFFSET_R10(%rsp), %r10
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	movq IOFFSET_R11(%rsp), %r11
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#ifdef CONFIG_DEBUG_ALLREGS	
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	movq IOFFSET_RBX(%rsp), %rbx
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	movq IOFFSET_RBP(%rsp), %rbp
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	movq IOFFSET_R12(%rsp), %r12
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	movq IOFFSET_R13(%rsp), %r13
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	movq IOFFSET_R14(%rsp), %r14
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	movq IOFFSET_R15(%rsp), %r15
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#endif
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.endm
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#ifdef CONFIG_DEBUG_ALLREGS
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# define INTERRUPT_ALIGN 256
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#else
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# define INTERRUPT_ALIGN 128
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#endif
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## Declare interrupt handlers
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#
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# Declare interrupt handlers for n interrupt
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# vectors starting at vector i.
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#
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# The handlers call exc_dispatch().
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#
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.macro handler i n
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1021 jermar 222
	/*
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	 * Choose between version with error code and version without error code.
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	 * Both versions have to be of the same size. amd64 assembly is, however,
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	 * a little bit tricky. For instance, subq $0x80, %rsp and subq $0x78, %rsp
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	 * can result in two instructions with different op-code lengths.
1121 jermar 227
	 * Therefore we align the interrupt handlers.
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	 */
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	.iflt \i-32
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		.if (1 << \i) & ERROR_WORD_INTERRUPT_LIST
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			/*
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			 * Version with error word.
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			 */
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			subq $IREGISTER_SPACE, %rsp
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		.else
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			/*
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			 * Version without error word,
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			 */
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			subq $(IREGISTER_SPACE+8), %rsp
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		.endif
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	.else
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		/*
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		 * Version without error word,
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		 */
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		subq $(IREGISTER_SPACE+8), %rsp
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	.endif	
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1021 jermar 249
	save_all_gpr
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1021 jermar 251
	movq $(\i), %rdi   	# %rdi - first parameter
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	movq %rsp, %rsi   	# %rsi - pointer to istate
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	call exc_dispatch 	# exc_dispatch(i, istate)
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799 palkovsky 255
	restore_all_gpr
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	# $8 = Skip error word
1021 jermar 257
	addq $(IREGISTER_SPACE+8), %rsp
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	iretq
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1094 palkovsky 260
	.align INTERRUPT_ALIGN
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	.if (\n-\i)-1
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	handler "(\i+1)",\n
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	.endif
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.endm
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.align INTERRUPT_ALIGN
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interrupt_handlers:
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h_start:
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	handler 0 IDT_ITEMS
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h_end:
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224 palkovsky 272
 
803 palkovsky 273
syscall_entry:
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	# Switch to hidden gs	
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	swapgs
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	# %gs:0 now points to pointer to stack page
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	mov %gs:0, %r10     # We have a ptr to stack page in r10
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	addq $PAGE_SIZE-16, %r10 # We need some space to store old %sp
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	movq %rsp, 0(%r10)  # Save old stack pointer to stack
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	movq %r10, %rsp     # Change to new stack
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	pushq %rcx          # Return address
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	pushq %r11          # Save flags
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285
	# Switch back to remain consistent
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	swapgs 
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955 palkovsky 288
	sti
806 palkovsky 289
	movq %r9, %rcx      # Exchange last parameter as a third
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803 palkovsky 291
	call syscall_handler
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	cli                 # We will be touching stack pointer
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806 palkovsky 294
	popq %r11
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	popq %rcx
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	movq 0(%rsp), %rsp
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	sysretq
803 palkovsky 298
 
1278 palkovsky 299
 
224 palkovsky 300
.data
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.global interrupt_handler_size
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820 jermar 303
interrupt_handler_size: .quad (h_end-h_start)/IDT_ITEMS