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206 palkovsky 1
/*
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 * Copyright (C) 2005 Ondrej Palkovsky
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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#include <arch.h>
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#include <arch/types.h>
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#include <config.h>
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#include <proc/thread.h>
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#include <arch/ega.h>
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#include <genarch/i8042/i8042.h>
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#include <arch/i8254.h>
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#include <arch/i8259.h>
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#include <arch/bios/bios.h>
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#include <arch/mm/memory_init.h>
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#include <arch/cpu.h>
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#include <print.h>
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#include <arch/cpuid.h>
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#include <genarch/acpi/acpi.h>
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#include <panic.h>
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#include <interrupt.h>
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#include <arch/syscall.h>
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#include <arch/debugger.h>
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#include <syscall/syscall.h>
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/** Disable I/O on non-privileged levels
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 *
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 * Clean IOPL(12,13) and NT(14) flags in EFLAGS register
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 */
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static void clean_IOPL_NT_flags(void)
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{
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    asm
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    (
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        "pushfq;"
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        "pop %%rax;"
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        "and $~(0x7000),%%rax;"
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        "pushq %%rax;"
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        "popfq;"
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        :
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        :
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        :"%rax"
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    );
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}
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/** Disable alignment check
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 *
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 * Clean AM(18) flag in CR0 register
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 */
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static void clean_AM_flag(void)
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{
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    asm
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    (
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        "mov %%cr0,%%rax;"
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        "and $~(0x40000),%%rax;"
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        "mov %%rax,%%cr0;"
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        :
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        :
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        :"%rax"
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    );
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}
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void arch_pre_mm_init(void)
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{
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    struct cpu_info cpuid_s;
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    cpuid(AMD_CPUID_EXTENDED,&cpuid_s);
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    if (! (cpuid_s.cpuid_edx & (1<<AMD_EXT_NOEXECUTE)))
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        panic("Processor does not support No-execute pages.\n");
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    cpuid(INTEL_CPUID_STANDARD,&cpuid_s);
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    if (! (cpuid_s.cpuid_edx & (1<<INTEL_FXSAVE)))
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        panic("Processor does not support FXSAVE/FXRESTORE.\n");
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    if (! (cpuid_s.cpuid_edx & (1<<INTEL_SSE2)))
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        panic("Processor does not support SSE2 instructions.\n");
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    /* Enable No-execute pages */
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    set_efer_flag(AMD_NXE_FLAG);
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    /* Enable FPU */
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    cpu_setup_fpu();
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    /* Initialize segmentation */
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    pm_init();
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        /* Disable I/O on nonprivileged levels
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     * clear the NT(nested-thread) flag
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     */
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    clean_IOPL_NT_flags();
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    /* Disable alignment check */
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    clean_AM_flag();
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    if (config.cpu_active == 1) {
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        bios_init();
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        i8259_init();   /* PIC */
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        i8254_init();   /* hard clock */
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        #ifdef CONFIG_SMP
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        exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown",
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                 tlb_shootdown_ipi);
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        #endif /* CONFIG_SMP */
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    }
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}
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void arch_post_mm_init(void)
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{
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    if (config.cpu_active == 1) {
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        ega_init(); /* video */
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        /* Enable debugger */
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        debugger_init();
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    }
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    /* Setup fast SYSCALL/SYSRET */
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    syscall_setup_cpu();
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}
242 palkovsky 143
 
503 jermar 144
void arch_pre_smp_init(void)
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{
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    if (config.cpu_active == 1) {
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        memory_print_map();
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458 decky 149
        #ifdef CONFIG_SMP
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        acpi_init();
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        #endif /* CONFIG_SMP */
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    }
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}
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503 jermar 155
void arch_post_smp_init(void)
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{
894 jermar 157
    i8042_init();   /* keyboard controller */
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}
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242 palkovsky 160
void calibrate_delay_loop(void)
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{
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    i8254_calibrate_delay_loop();
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    i8254_normal_operation();
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}
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/** Set thread-local-storage pointer
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 *
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 * TLS pointer is set in FS register. Unfortunately the 64-bit
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 * part can be set only in CPL0 mode.
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 *
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 * The specs say, that on %fs:0 there is stored contents of %fs register,
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 * we need not to go to CPL0 to read it.
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 */
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__native sys_tls_set(__native addr)
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{
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    THREAD->tls = addr;
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    write_msr(AMD_MSR_FS, addr);
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    return 0;
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}