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173 jermar 1
/*
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 * Copyright (c) 2005 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup amd64  
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 * @{
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 */
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/** @file
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 */
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#ifndef KERN_amd64_ASM_H_
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#define KERN_amd64_ASM_H_
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#include <config.h>
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extern void asm_delay_loop(uint32_t t);
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extern void asm_fake_loop(uint32_t t);
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/** Return base address of current stack.
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 *
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 * Return the base address of the current stack.
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 * The stack is assumed to be STACK_SIZE bytes long.
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 * The stack must start on page boundary.
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 */
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static inline uintptr_t get_stack_base(void)
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{
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    uintptr_t v;
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    asm volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((uint64_t)STACK_SIZE-1)));
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    return v;
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}
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static inline void cpu_sleep(void)
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{
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    asm volatile ("hlt\n");
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}
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static inline void cpu_halt(void)
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{
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    asm volatile ("hlt\n");
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}
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/** Byte from port
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 *
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 * Get byte from port
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 *
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 * @param port Port to read from
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 * @return Value read
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 */
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static inline uint8_t inb(uint16_t port)
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{
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    uint8_t val;
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    asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port));
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    return val;
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}
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/** Byte to port
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 *
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 * Output byte to port
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 *
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 * @param port Port to write to
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 * @param val Value to write
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 */
2453 jermar 91
static inline void outb(uint16_t port, uint8_t val)
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{
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    asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port));
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}
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/** Swap Hidden part of GS register with visible one */
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static inline void swapgs(void)
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{
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    asm volatile("swapgs");
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}
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/** Enable interrupts.
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 *
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 * Enable interrupts and return previous
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 * value of EFLAGS.
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 *
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 * @return Old interrupt priority level.
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 */
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static inline ipl_t interrupts_enable(void) {
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    ipl_t v;
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    __asm__ volatile (
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        "pushfq\n"
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        "popq %0\n"
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        "sti\n"
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        : "=r" (v)
116
    );
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    return v;
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}
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/** Disable interrupts.
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 *
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 * Disable interrupts and return previous
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 * value of EFLAGS.
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 *
125
 * @return Old interrupt priority level.
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 */
413 jermar 127
static inline ipl_t interrupts_disable(void) {
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    ipl_t v;
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    __asm__ volatile (
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        "pushfq\n"
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        "popq %0\n"
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        "cli\n"
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        : "=r" (v)
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        );
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    return v;
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}
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/** Restore interrupt priority level.
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 *
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 * Restore EFLAGS.
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 *
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 * @param ipl Saved interrupt priority level.
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 */
413 jermar 144
static inline void interrupts_restore(ipl_t ipl) {
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    __asm__ volatile (
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        "pushq %0\n"
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        "popfq\n"
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        : : "r" (ipl)
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        );
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}
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/** Return interrupt priority level.
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 *
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 * Return EFLAFS.
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 *
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 * @return Current interrupt priority level.
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 */
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static inline ipl_t interrupts_read(void) {
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    ipl_t v;
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    __asm__ volatile (
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        "pushfq\n"
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        "popq %0\n"
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        : "=r" (v)
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    );
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    return v;
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}
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803 palkovsky 168
/** Write to MSR */
1780 jermar 169
static inline void write_msr(uint32_t msr, uint64_t value)
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{
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    __asm__ volatile (
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        "wrmsr;" : : "c" (msr),
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        "a" ((uint32_t)(value)),
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        "d" ((uint32_t)(value >> 32))
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        );
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}
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static inline unative_t read_msr(uint32_t msr)
803 palkovsky 179
{
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    uint32_t ax, dx;
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    __asm__ volatile (
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        "rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)
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        );
1780 jermar 185
    return ((uint64_t)dx << 32) | ax;
803 palkovsky 186
}
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/** Enable local APIC
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 *
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 * Enable local APIC in MSR.
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 */
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static inline void enable_l_apic_in_msr()
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{
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    __asm__ volatile (
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        "movl $0x1b, %%ecx\n"
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        "rdmsr\n"
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        "orl $(1<<11),%%eax\n"
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        "orl $(0xfee00000),%%eax\n"
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        "wrmsr\n"
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        :
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        :
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        :"%eax","%ecx","%edx"
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        );
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}
206
 
1780 jermar 207
static inline uintptr_t * get_ip()
581 palkovsky 208
{
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    uintptr_t *ip;
581 palkovsky 210
 
211
    __asm__ volatile (
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        "mov %%rip, %0"
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        : "=r" (ip)
214
        );
215
    return ip;
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}
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597 jermar 218
/** Invalidate TLB Entry.
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 *
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 * @param addr Address on a page whose TLB entry is to be invalidated.
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 */
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static inline void invlpg(uintptr_t addr)
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{
1780 jermar 224
    __asm__ volatile ("invlpg %0\n" :: "m" (*((unative_t *)addr)));
597 jermar 225
}
581 palkovsky 226
 
1186 jermar 227
/** Load GDTR register from memory.
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 *
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 * @param gdtr_reg Address of memory from where to load GDTR.
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 */
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static inline void gdtr_load(struct ptr_16_64 *gdtr_reg)
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{
1251 jermar 233
    __asm__ volatile ("lgdtq %0\n" : : "m" (*gdtr_reg));
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}
235
 
236
/** Store GDTR register to memory.
237
 *
238
 * @param gdtr_reg Address of memory to where to load GDTR.
239
 */
240
static inline void gdtr_store(struct ptr_16_64 *gdtr_reg)
241
{
1251 jermar 242
    __asm__ volatile ("sgdtq %0\n" : : "m" (*gdtr_reg));
1186 jermar 243
}
244
 
245
/** Load IDTR register from memory.
246
 *
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 * @param idtr_reg Address of memory from where to load IDTR.
248
 */
249
static inline void idtr_load(struct ptr_16_64 *idtr_reg)
250
{
1251 jermar 251
    __asm__ volatile ("lidtq %0\n" : : "m" (*idtr_reg));
1186 jermar 252
}
253
 
254
/** Load TR from descriptor table.
255
 *
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 * @param sel Selector specifying descriptor of TSS segment.
257
 */
1780 jermar 258
static inline void tr_load(uint16_t sel)
1186 jermar 259
{
260
    __asm__ volatile ("ltr %0" : : "r" (sel));
261
}
262
 
1780 jermar 263
#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
1072 palkovsky 264
    { \
1780 jermar 265
    unative_t res; \
1072 palkovsky 266
    __asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \
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    return res; \
268
    }
269
 
1780 jermar 270
#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
1072 palkovsky 271
    { \
272
    __asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \
273
    }
274
 
2452 jermar 275
GEN_READ_REG(cr0)
276
GEN_READ_REG(cr2)
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GEN_READ_REG(cr3)
278
GEN_WRITE_REG(cr3)
1072 palkovsky 279
 
2452 jermar 280
GEN_READ_REG(dr0)
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GEN_READ_REG(dr1)
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GEN_READ_REG(dr2)
283
GEN_READ_REG(dr3)
284
GEN_READ_REG(dr6)
285
GEN_READ_REG(dr7)
1072 palkovsky 286
 
2452 jermar 287
GEN_WRITE_REG(dr0)
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GEN_WRITE_REG(dr1)
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GEN_WRITE_REG(dr2)
290
GEN_WRITE_REG(dr3)
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GEN_WRITE_REG(dr6)
292
GEN_WRITE_REG(dr7)
1072 palkovsky 293
 
206 palkovsky 294
extern size_t interrupt_handler_size;
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extern void interrupt_handlers(void);
296
 
173 jermar 297
#endif
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1888 jermar 299
/** @}
1702 cejka 300
 */