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1816 decky 1
/*
2071 jermar 2
 * Copyright (c) 2001-2004 Jakub Jermar
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 * Copyright (c) 2005 Sergey Bondari
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 * Copyright (c) 2006 Martin Decky
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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1952 jermar 31
/** @addtogroup ia32xen
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 * @{
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 */
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/** @file
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 */
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1952 jermar 37
#ifndef KERN_ia32xen_ASM_H_
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#define KERN_ia32xen_ASM_H_
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#include <arch/pm.h>
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#include <arch/types.h>
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#include <arch/barrier.h>
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#include <config.h>
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extern void enable_l_apic_in_msr(void);
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extern void asm_delay_loop(uint32_t t);
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extern void asm_fake_loop(uint32_t t);
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/** Halt CPU
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 *
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 * Halt the current CPU until interrupt event.
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 */
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#define cpu_halt() ((void) 0)
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#define cpu_sleep() ((void) 0)
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#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
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    { \
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    unative_t res; \
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    asm volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
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    return res; \
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    }
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#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
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    { \
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    asm volatile ("movl %0, %%" #reg : : "r" (regn)); \
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    }
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GEN_READ_REG(cr0);
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GEN_READ_REG(cr2);
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GEN_READ_REG(dr0);
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GEN_READ_REG(dr1);
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GEN_READ_REG(dr2);
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GEN_READ_REG(dr3);
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GEN_READ_REG(dr6);
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GEN_READ_REG(dr7);
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GEN_WRITE_REG(dr0);
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GEN_WRITE_REG(dr1);
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GEN_WRITE_REG(dr2);
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GEN_WRITE_REG(dr3);
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GEN_WRITE_REG(dr6);
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GEN_WRITE_REG(dr7);
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/** Byte to port
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 *
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 * Output byte to port
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 *
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 * @param port Port to write to
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 * @param val Value to write
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 */
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static inline void outb(uint16_t port, uint8_t val) { asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
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/** Word to port
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 *
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 * Output word to port
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 *
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 * @param port Port to write to
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 * @param val Value to write
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 */
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static inline void outw(uint16_t port, uint16_t val) { asm volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
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/** Double word to port
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 *
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 * Output double word to port
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 *
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 * @param port Port to write to
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 * @param val Value to write
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 */
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static inline void outl(uint16_t port, uint32_t val) { asm volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
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/** Byte from port
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 *
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 * Get byte from port
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 *
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 * @param port Port to read from
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 * @return Value read
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 */
2082 decky 122
static inline uint8_t inb(uint16_t port) { uint8_t val; asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
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/** Word from port
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 *
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 * Get word from port
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 *
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 * @param port Port to read from
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 * @return Value read
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 */
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static inline uint16_t inw(uint16_t port) { uint16_t val; asm volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }
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/** Double word from port
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 *
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 * Get double word from port
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 *
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 * @param port Port to read from
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 * @return Value read
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 */
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static inline uint32_t inl(uint16_t port) { uint32_t val; asm volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
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/** Enable interrupts.
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 *
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 * Enable interrupts and return previous
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 * value of EFLAGS.
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 *
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 * @return Old interrupt priority level.
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 */
149
static inline ipl_t interrupts_enable(void)
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{
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    // FIXME SMP
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    ipl_t v = shared_info.vcpu_info[0].evtchn_upcall_mask;
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    write_barrier();
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    shared_info.vcpu_info[0].evtchn_upcall_mask = 0;
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    write_barrier();
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    if (shared_info.vcpu_info[0].evtchn_upcall_pending)
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        force_evtchn_callback();
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1816 decky 160
    return v;
161
}
162
 
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/** Disable interrupts.
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 *
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 * Disable interrupts and return previous
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 * value of EFLAGS.
167
 *
168
 * @return Old interrupt priority level.
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 */
170
static inline ipl_t interrupts_disable(void)
171
{
1830 decky 172
    // FIXME SMP
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174
    ipl_t v = shared_info.vcpu_info[0].evtchn_upcall_mask;
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    shared_info.vcpu_info[0].evtchn_upcall_mask = 1;
176
    write_barrier();
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    return v;
179
}
180
 
181
/** Restore interrupt priority level.
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 *
183
 * Restore EFLAGS.
184
 *
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 * @param ipl Saved interrupt priority level.
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 */
187
static inline void interrupts_restore(ipl_t ipl)
188
{
1830 decky 189
    if (ipl == 0)
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        interrupts_enable();
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    else
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        interrupts_disable();
1816 decky 193
}
194
 
195
/** Return interrupt priority level.
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 *
197
 * @return EFLAFS.
198
 */
199
static inline ipl_t interrupts_read(void)
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{
1830 decky 201
    // FIXME SMP
202
 
203
    return shared_info.vcpu_info[0].evtchn_upcall_mask;
1816 decky 204
}
205
 
206
/** Return base address of current stack
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 *
208
 * Return the base address of the current stack.
209
 * The stack is assumed to be STACK_SIZE bytes long.
210
 * The stack must start on page boundary.
211
 */
212
static inline uintptr_t get_stack_base(void)
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{
214
    uintptr_t v;
215
 
2082 decky 216
    asm volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
1816 decky 217
 
218
    return v;
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}
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/** Return current IP address */
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static inline uintptr_t * get_ip()
223
{
224
    uintptr_t *ip;
225
 
2082 decky 226
    asm volatile (
1816 decky 227
        "mov %%eip, %0"
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        : "=r" (ip)
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        );
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    return ip;
231
}
232
 
233
/** Invalidate TLB Entry.
234
 *
235
 * @param addr Address on a page whose TLB entry is to be invalidated.
236
 */
237
static inline void invlpg(uintptr_t addr)
238
{
2082 decky 239
    asm volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr));
1816 decky 240
}
241
 
242
/** Load GDTR register from memory.
243
 *
244
 * @param gdtr_reg Address of memory from where to load GDTR.
245
 */
246
static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
247
{
2082 decky 248
    asm volatile ("lgdtl %0\n" : : "m" (*gdtr_reg));
1816 decky 249
}
250
 
251
/** Store GDTR register to memory.
252
 *
253
 * @param gdtr_reg Address of memory to where to load GDTR.
254
 */
255
static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
256
{
2082 decky 257
    asm volatile ("sgdtl %0\n" : : "m" (*gdtr_reg));
1816 decky 258
}
259
 
260
/** Load TR from descriptor table.
261
 *
262
 * @param sel Selector specifying descriptor of TSS segment.
263
 */
264
static inline void tr_load(uint16_t sel)
265
{
2082 decky 266
    asm volatile ("ltr %0" : : "r" (sel));
1816 decky 267
}
268
 
269
#endif
270
 
271
/** @}
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 */