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2468 jermar 1
/*
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 * Copyright (c) 2007 Pavel Jancik
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 * Copyright (c) 2007 Michal Kebrt
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup arm32boot
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 * @{
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 */
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/** @file
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 *  @brief Memory management used while booting the kernel.
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 *
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 *  So called "section" paging is used while booting the kernel. The term
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 *  "section" comes from the ARM architecture specification and stands for the
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 *  following: one-level paging, 1MB sized pages, 4096 entries in the page
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 *  table.
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 */
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#ifndef BOOT_arm32__MM_H
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#define BOOT_arm32__MM_H
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#ifndef __ASM__
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#include "types.h"
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#endif
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/** Frame width. */
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#define FRAME_WIDTH         20
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/** Frame size. */
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#define FRAME_SIZE          (1 << FRAME_WIDTH)
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/** Page size in 2-level paging which is switched on later after the kernel
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 * initialization.
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 */
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#define KERNEL_PAGE_SIZE        (1 << 12)
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#ifndef __ASM__
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/** Converts kernel address to physical address. */
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#   define KA2PA(x)         (((uintptr_t) (x)) - 0x80000000)
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/** Converts physical address to kernel address. */
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#   define PA2KA(x)         (((uintptr_t) (x)) + 0x80000000)
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#else
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#   define KA2PA(x)         ((x) - 0x80000000)
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#   define PA2KA(x)         ((x) + 0x80000000)
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#endif
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/** Number of entries in PTL0. */
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#define PTL0_ENTRIES            (1 << 12)   /* 4096 */
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/** Size of an entry in PTL0. */
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#define PTL0_ENTRY_SIZE         4
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/** Returns number of frame the address belongs to. */
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#define ADDR2PFN(addr)          (((uintptr_t) (addr)) >> FRAME_WIDTH)
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/** Describes "section" page table entry (one-level paging with 1MB sized pages). */  
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#define PTE_DESCRIPTOR_SECTION      0x2
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/** Page table access rights: user - no access, kernel - read/write. */
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#define PTE_AP_USER_NO_KERNEL_RW    0x1
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#ifndef __ASM__
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/** Page table level 0 entry - "section" format is used (one-level paging, 1MB
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 * sized pages). Used only while booting the kernel.
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 */
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typedef struct {
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    unsigned descriptor_type : 2;
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    unsigned bufferable : 1;
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    unsigned cacheable : 1;
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    unsigned impl_specific : 1;
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    unsigned domain : 4;
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    unsigned should_be_zero_1 : 1;
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    unsigned access_permission : 2;    
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    unsigned should_be_zero_2 : 8;
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    unsigned section_base_addr : 12;
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} __attribute__ ((packed)) pte_level0_section_t;
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/** Page table that holds 1:1 virtual to physical mapping used while booting the
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 * kernel.
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 */
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extern pte_level0_section_t page_table[PTL0_ENTRIES];
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extern void mmu_start(void);
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/** Enables paging. */
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static inline void enable_paging()
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{
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    /* c3 - each two bits controls access to the one of domains (16)
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     *      0b01 - behave as a client (user) of a domain
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     */
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    asm volatile (
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        /* behave as a client of domains */
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        "ldr r0, =0x55555555\n"
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        "mcr p15, 0, r0, c3, c0, 0\n"
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        /* current settings */
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        "mrc p15, 0, r0, c1, c0, 0\n"
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        /* mask to enable paging */
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        "ldr r1, =0x00000001\n"
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        "orr r0, r0, r1\n"
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        /* store settings */
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        "mcr p15, 0, r0, c1, c0, 0\n"
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        :
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        :
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        : "r0", "r1"
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    );
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}
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/** Sets the address of level 0 page table to CP15 register 2.
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 *
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 * @param pt Address of a page table to set.
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 */  
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static inline void set_ptl0_address(pte_level0_section_t* pt)
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{
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    asm volatile (
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        "mcr p15, 0, %0, c2, c0, 0\n"
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        :
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        : "r" (pt)
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    );
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}
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#endif
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#endif
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/** @}
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 */
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