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173 jermar 1
/*
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 * Copyright (C) 2005 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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#ifndef __ia64_ASM_H__
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#define __ia64_ASM_H__
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747 jermar 32
#include <config.h>
173 jermar 33
#include <arch/types.h>
432 jermar 34
#include <arch/register.h>
173 jermar 35
 
180 jermar 36
/** Return base address of current stack
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 *
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 * Return the base address of the current stack.
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 * The stack is assumed to be STACK_SIZE long.
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 * The stack must start on page boundary.
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 */
173 jermar 42
static inline __address get_stack_base(void)
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{
180 jermar 44
    __u64 v;
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    __asm__ volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
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    return v;
173 jermar 49
}
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919 jermar 51
/** Return Processor State Register.
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 *
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 * @return PSR.
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 */
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static inline __u64 psr_read(void)
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{
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    __u64 v;
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    __asm__ volatile ("mov %0 = psr\n" : "=r" (v));
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    return v;
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}
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470 jermar 64
/** Read IVA (Interruption Vector Address).
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 *
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 * @return Return location of interruption vector table.
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 */
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static inline __u64 iva_read(void)
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{
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    __u64 v;
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    __asm__ volatile ("mov %0 = cr.iva\n" : "=r" (v));
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    return v;
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}
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/** Write IVA (Interruption Vector Address) register.
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 *
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 * @param New location of interruption vector table.
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 */
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static inline void iva_write(__u64 v)
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{
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    __asm__ volatile ("mov cr.iva = %0\n" : : "r" (v));
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}
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432 jermar 87
/** Read IVR (External Interrupt Vector Register).
431 jermar 88
 *
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 * @return Highest priority, pending, unmasked external interrupt vector.
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 */
432 jermar 91
static inline __u64 ivr_read(void)
431 jermar 92
{
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    __u64 v;
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432 jermar 95
    __asm__ volatile ("mov %0 = cr.ivr\n" : "=r" (v));
431 jermar 96
 
432 jermar 97
    return v;
431 jermar 98
}
195 vana 99
 
432 jermar 100
/** Write ITC (Interval Timer Counter) register.
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 *
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 * @param New counter value.
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 */
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static inline void itc_write(__u64 v)
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{
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    __asm__ volatile ("mov ar.itc = %0\n" : : "r" (v));
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}
431 jermar 108
 
432 jermar 109
/** Read ITC (Interval Timer Counter) register.
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 *
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 * @return Current counter value.
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 */
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static inline __u64 itc_read(void)
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{
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    __u64 v;
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    __asm__ volatile ("mov %0 = ar.itc\n" : "=r" (v));
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    return v;
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}
195 vana 121
 
432 jermar 122
/** Write ITM (Interval Timer Match) register.
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 *
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 * @param New match value.
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 */
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static inline void itm_write(__u64 v)
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{
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    __asm__ volatile ("mov cr.itm = %0\n" : : "r" (v));
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}
195 vana 130
 
1488 vana 131
/** Read ITM (Interval Timer Match) register.
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 *
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 * @return Match value.
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 */
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static inline __u64 itm_read(void)
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{
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    __u64 v;
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    __asm__ volatile ("mov %0 = cr.itm\n" : "=r" (v));
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141
    return v;
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}
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433 jermar 144
/** Read ITV (Interval Timer Vector) register.
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 *
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 * @return Current vector and mask bit.
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 */
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static inline __u64 itv_read(void)
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{
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    __u64 v;
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    __asm__ volatile ("mov %0 = cr.itv\n" : "=r" (v));
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154
    return v;
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}
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432 jermar 157
/** Write ITV (Interval Timer Vector) register.
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 *
433 jermar 159
 * @param New vector and mask bit.
432 jermar 160
 */
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static inline void itv_write(__u64 v)
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{
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    __asm__ volatile ("mov cr.itv = %0\n" : : "r" (v));
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}
238 vana 165
 
432 jermar 166
/** Write EOI (End Of Interrupt) register.
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 *
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 * @param This value is ignored.
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 */
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static inline void eoi_write(__u64 v)
171
{
172
    __asm__ volatile ("mov cr.eoi = %0\n" : : "r" (v));
173
}
174
 
175
/** Read TPR (Task Priority Register).
176
 *
177
 * @return Current value of TPR.
178
 */
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static inline __u64 tpr_read(void)
180
{
181
    __u64 v;
182
 
183
    __asm__ volatile ("mov %0 = cr.tpr\n"  : "=r" (v));
184
 
185
    return v;
186
}
187
 
188
/** Write TPR (Task Priority Register).
189
 *
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 * @param New value of TPR.
191
 */
192
static inline void tpr_write(__u64 v)
193
{
194
    __asm__ volatile ("mov cr.tpr = %0\n" : : "r" (v));
195
}
196
 
197
/** Disable interrupts.
198
 *
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 * Disable interrupts and return previous
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 * value of PSR.
201
 *
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 * @return Old interrupt priority level.
203
 */
204
static ipl_t interrupts_disable(void)
205
{
206
    __u64 v;
207
 
208
    __asm__ volatile (
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        "mov %0 = psr\n"
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        "rsm %1\n"
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        : "=r" (v)
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        : "i" (PSR_I_MASK)
213
    );
214
 
215
    return (ipl_t) v;
216
}
217
 
218
/** Enable interrupts.
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 *
220
 * Enable interrupts and return previous
221
 * value of PSR.
222
 *
223
 * @return Old interrupt priority level.
224
 */
225
static ipl_t interrupts_enable(void)
226
{
227
    __u64 v;
228
 
229
    __asm__ volatile (
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        "mov %0 = psr\n"
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        "ssm %1\n"
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        ";;\n"
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        "srlz.d\n"
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        : "=r" (v)
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        : "i" (PSR_I_MASK)
236
    );
237
 
238
    return (ipl_t) v;
239
}
240
 
241
/** Restore interrupt priority level.
242
 *
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 * Restore PSR.
244
 *
245
 * @param ipl Saved interrupt priority level.
246
 */
247
static inline void interrupts_restore(ipl_t ipl)
248
{
472 jermar 249
    if (ipl & PSR_I_MASK)
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        (void) interrupts_enable();
251
    else
252
        (void) interrupts_disable();
432 jermar 253
}
254
 
255
/** Return interrupt priority level.
256
 *
257
 * @return PSR.
258
 */
259
static inline ipl_t interrupts_read(void)
260
{
919 jermar 261
    return (ipl_t) psr_read();
432 jermar 262
}
263
 
746 jermar 264
/** Disable protection key checking. */
265
static inline void pk_disable(void)
266
{
267
    __asm__ volatile ("rsm %0\n" : : "i" (PSR_PK_MASK));
268
}
269
 
432 jermar 270
extern void cpu_halt(void);
271
extern void cpu_sleep(void);
272
extern void asm_delay_loop(__u32 t);
238 vana 273
 
1078 jermar 274
extern void switch_to_userspace(__address entry, __address sp, __address bsp, __address uspace_uarg, __u64 ipsr, __u64 rsc);
919 jermar 275
 
173 jermar 276
#endif