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1911 jermar 1
/*
2071 jermar 2
 * Copyright (c) 2006 Jakub Jermar
1911 jermar 3
 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup sparc64
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 * @{
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 */
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/**
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 * @file
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 * @brief   PCI driver.
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 */
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#include <arch/drivers/pci.h>
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#include <genarch/ofw/ofw_tree.h>
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#include <arch/trap/interrupt.h>
2089 decky 40
#include <mm/page.h>
1911 jermar 41
#include <mm/slab.h>
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#include <arch/types.h>
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#include <debug.h>
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#include <print.h>
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#include <func.h>
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#include <arch/asm.h>
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#define PCI_SABRE_REGS_REG  0
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#define PCI_SABRE_IMAP_BASE 0x200
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#define PCI_SABRE_ICLR_BASE 0x300
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1984 jermar 53
#define PCI_PSYCHO_REGS_REG 2   
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#define PCI_PSYCHO_IMAP_BASE    0x200
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#define PCI_PSYCHO_ICLR_BASE    0x300   
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1911 jermar 58
static pci_t *pci_sabre_init(ofw_tree_node_t *node);
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static void pci_sabre_enable_interrupt(pci_t *pci, int inr);
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static void pci_sabre_clear_interrupt(pci_t *pci, int inr);
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1984 jermar 62
static pci_t *pci_psycho_init(ofw_tree_node_t *node);
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static void pci_psycho_enable_interrupt(pci_t *pci, int inr);
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static void pci_psycho_clear_interrupt(pci_t *pci, int inr);
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1911 jermar 66
/** PCI operations for Sabre model. */
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static pci_operations_t pci_sabre_ops = {
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    .enable_interrupt = pci_sabre_enable_interrupt,
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    .clear_interrupt = pci_sabre_clear_interrupt
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};
1984 jermar 71
/** PCI operations for Psycho model. */
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static pci_operations_t pci_psycho_ops = {
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    .enable_interrupt = pci_psycho_enable_interrupt,
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    .clear_interrupt = pci_psycho_clear_interrupt
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};
1911 jermar 76
 
1984 jermar 77
/** Initialize PCI controller (model Sabre).
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 *
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 * @param node OpenFirmware device tree node of the Sabre.
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 *
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 * @return Address of the initialized PCI structure.
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 */
1911 jermar 83
pci_t *pci_sabre_init(ofw_tree_node_t *node)
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{
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    pci_t *pci;
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    ofw_tree_property_t *prop;
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    /*
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     * Get registers.
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     */
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    prop = ofw_tree_getprop(node, "reg");
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    if (!prop || !prop->value)
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        return NULL;
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    ofw_upa_reg_t *reg = prop->value;
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    count_t regs = prop->size / sizeof(ofw_upa_reg_t);
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    if (regs < PCI_SABRE_REGS_REG + 1)
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        return NULL;
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    uintptr_t paddr;
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    if (!ofw_upa_apply_ranges(node->parent, &reg[PCI_SABRE_REGS_REG], &paddr))
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        return NULL;
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    pci = (pci_t *) malloc(sizeof(pci_t), FRAME_ATOMIC);
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    if (!pci)
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        return NULL;
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    pci->model = PCI_SABRE;
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    pci->op = &pci_sabre_ops;
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    pci->reg = (uint64_t *) hw_map(paddr, reg[PCI_SABRE_REGS_REG].size);
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    return pci;
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}
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1984 jermar 116
 
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/** Initialize the Psycho PCI controller.
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 *
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 * @param node OpenFirmware device tree node of the Psycho.
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 *
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 * @return Address of the initialized PCI structure.
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 */
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pci_t *pci_psycho_init(ofw_tree_node_t *node)
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{
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    pci_t *pci;
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    ofw_tree_property_t *prop;
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    /*
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     * Get registers.
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     */
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    prop = ofw_tree_getprop(node, "reg");
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    if (!prop || !prop->value)
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        return NULL;
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    ofw_upa_reg_t *reg = prop->value;
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    count_t regs = prop->size / sizeof(ofw_upa_reg_t);
137
 
138
    if (regs < PCI_PSYCHO_REGS_REG + 1)
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        return NULL;
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    uintptr_t paddr;
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    if (!ofw_upa_apply_ranges(node->parent, &reg[PCI_PSYCHO_REGS_REG], &paddr))
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        return NULL;
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    pci = (pci_t *) malloc(sizeof(pci_t), FRAME_ATOMIC);
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    if (!pci)
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        return NULL;
148
 
149
    pci->model = PCI_PSYCHO;
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    pci->op = &pci_psycho_ops;
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    pci->reg = (uint64_t *) hw_map(paddr, reg[PCI_PSYCHO_REGS_REG].size);
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153
    return pci;
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}
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1911 jermar 156
void pci_sabre_enable_interrupt(pci_t *pci, int inr)
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{
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    pci->reg[PCI_SABRE_IMAP_BASE + (inr & INO_MASK)] |= IMAP_V_MASK;
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}
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161
void pci_sabre_clear_interrupt(pci_t *pci, int inr)
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{
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    pci->reg[PCI_SABRE_ICLR_BASE + (inr & INO_MASK)] = 0;
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}
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1984 jermar 166
void pci_psycho_enable_interrupt(pci_t *pci, int inr)
167
{
168
    pci->reg[PCI_PSYCHO_IMAP_BASE + (inr & INO_MASK)] |= IMAP_V_MASK;
169
}
170
 
171
void pci_psycho_clear_interrupt(pci_t *pci, int inr)
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{
173
    pci->reg[PCI_PSYCHO_ICLR_BASE + (inr & INO_MASK)] = 0;
174
}
175
 
1911 jermar 176
/** Initialize PCI controller. */
177
pci_t *pci_init(ofw_tree_node_t *node)
178
{
179
    ofw_tree_property_t *prop;
180
 
181
    /*
182
     * First, verify this is a PCI node.
183
     */
184
    ASSERT(strcmp(ofw_tree_node_name(node), "pci") == 0);
185
 
186
    /*
187
     * Determine PCI controller model.
188
     */
189
    prop = ofw_tree_getprop(node, "model");
190
    if (!prop || !prop->value)
191
        return NULL;
192
 
193
    if (strcmp(prop->value, "SUNW,sabre") == 0) {
194
        /*
195
         * PCI controller Sabre.
196
         * This model is found on UltraSPARC IIi based machines.
197
         */
198
        return pci_sabre_init(node);
1984 jermar 199
    } else if (strcmp(prop->value, "SUNW,psycho") == 0) {
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        /*
201
         * PCI controller Psycho.
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         * Used on UltraSPARC II based processors, for instance,
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         * on Ultra 60.
204
         */
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        return pci_psycho_init(node);
1911 jermar 206
    } else {
207
        /*
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         * Unsupported model.
209
         */
210
        printf("Unsupported PCI controller model (%s).\n", prop->value);
211
    }
212
 
213
    return NULL;
214
}
215
 
216
void pci_enable_interrupt(pci_t *pci, int inr)
217
{
218
    ASSERT(pci->model);
219
    ASSERT(pci->op && pci->op->enable_interrupt);
220
    pci->op->enable_interrupt(pci, inr);
221
}
222
 
223
void pci_clear_interrupt(pci_t *pci, int inr)
224
{
225
    ASSERT(pci->model);
226
    ASSERT(pci->op && pci->op->clear_interrupt);
227
    pci->op->clear_interrupt(pci, inr);
228
}
229
 
230
/** @}
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 */