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864 jermar 1
/*
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 * Copyright (c) 2006 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup sparc64interrupt
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 * @{
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 */
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/**
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 * @file
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 * @brief This file contains fast MMU trap handlers.
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 */
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#ifndef KERN_sparc64_MMU_TRAP_H_
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#define KERN_sparc64_MMU_TRAP_H_
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#include <arch/stack.h>
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#include <arch/regdef.h>
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#include <arch/mm/tlb.h>
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#include <arch/mm/mmu.h>
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#include <arch/mm/tte.h>
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#include <arch/trap/regwin.h>
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#ifdef CONFIG_TSB
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#include <arch/mm/tsb.h>
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#endif
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#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64
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#define TT_FAST_DATA_ACCESS_MMU_MISS        0x68
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#define TT_FAST_DATA_ACCESS_PROTECTION      0x6c
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#define FAST_MMU_HANDLER_SIZE           128
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#ifdef __ASM__
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.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
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    /*
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     * First, try to refill TLB from TSB.
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     */
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#ifdef CONFIG_TSB
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    ldxa [%g0] ASI_IMMU, %g1            ! read TSB Tag Target Register
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    ldxa [%g0] ASI_IMMU_TSB_8KB_PTR_REG, %g2    ! read TSB 8K Pointer
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    ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4        ! 16-byte atomic load into %g4 and %g5
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    cmp %g1, %g4                    ! is this the entry we are looking for?
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    bne,pn %xcc, 0f
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    nop
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    stxa %g5, [%g0] ASI_ITLB_DATA_IN_REG        ! copy mapping from ITSB to ITLB
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    retry
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#endif
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0:
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    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
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    PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
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.endm
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.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl
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    /*
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     * First, try to refill TLB from TSB.
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     */
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#ifdef CONFIG_TSB
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    ldxa [%g0] ASI_DMMU, %g1            ! read TSB Tag Target Register
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    srlx %g1, TSB_TAG_TARGET_CONTEXT_SHIFT, %g2 ! is this a kernel miss?
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    brz,pn %g2, 0f
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    ldxa [%g0] ASI_DMMU_TSB_8KB_PTR_REG, %g3    ! read TSB 8K Pointer
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    ldda [%g3] ASI_NUCLEUS_QUAD_LDD, %g4        ! 16-byte atomic load into %g4 and %g5
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    cmp %g1, %g4                    ! is this the entry we are looking for?
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    bne,pn %xcc, 0f
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    nop
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    stxa %g5, [%g0] ASI_DTLB_DATA_IN_REG        ! copy mapping from DTSB to DTLB
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    retry
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#endif
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    /*
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     * Second, test if it is the portion of the kernel address space
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     * which is faulting. If that is the case, immediately create
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     * identity mapping for that page in DTLB. VPN 0 is excluded from
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     * this treatment.
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     *
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     * Note that branch-delay slots are used in order to save space.
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     */
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0:
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    sethi %hi(fast_data_access_mmu_miss_data_hi), %g7
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    wr %g0, ASI_DMMU, %asi
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    ldxa [VA_DMMU_TAG_ACCESS] %asi, %g1     ! read the faulting Context and VPN
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    set TLB_TAG_ACCESS_CONTEXT_MASK, %g2
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    andcc %g1, %g2, %g3             ! get Context
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    bnz %xcc, 0f                    ! Context is non-zero
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    andncc %g1, %g2, %g3                ! get page address into %g3
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    bz  %xcc, 0f                    ! page address is zero
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    ldx [%g7 + %lo(end_of_identity)], %g4
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    cmp %g3, %g4
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    bgeu %xcc, 0f
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    ldx [%g7 + %lo(kernel_8k_tlb_data_template)], %g2
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    add %g3, %g2, %g2
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    stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG        ! identity map the kernel page
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    retry
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    /*
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     * Third, catch and handle special cases when the trap is caused by
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     * the userspace register window spill or fill handler. In case
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     * one of these two traps caused this trap, we just lower the trap
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     * level and service the DTLB miss. In the end, we restart
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     * the offending SAVE or RESTORE.
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     */
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0:
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.if (\tl > 0)
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    wrpr %g0, 1, %tl
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.endif
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    /*
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     * Switch from the MM globals.
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     */
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    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
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    /*
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     * Read the Tag Access register for the higher-level handler.
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     * This is necessary to survive nested DTLB misses.
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     */
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    ldxa [VA_DMMU_TAG_ACCESS] %asi, %g2
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146
    /*
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     * g2 will be passed as an argument to fast_data_access_mmu_miss().
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     */
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    PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
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.endm
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.macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl
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    /*
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     * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER.
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     */
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.if (\tl > 0)
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    wrpr %g0, 1, %tl
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.endif
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    /*
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     * Switch from the MM globals.
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     */
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    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
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    /*
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     * Read the Tag Access register for the higher-level handler.
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     * This is necessary to survive nested DTLB misses.
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     */
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    mov VA_DMMU_TAG_ACCESS, %g2
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    ldxa [%g2] ASI_DMMU, %g2
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    /*
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     * g2 will be passed as an argument to fast_data_access_mmu_miss().
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     */
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    PREEMPTIBLE_HANDLER fast_data_access_protection
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.endm
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#endif /* __ASM__ */
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#endif
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/** @}
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 */