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1 jermar 1
#
2071 jermar 2
# Copyright (c) 2003-2004 Jakub Jermar
1 jermar 3
# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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#
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# - Redistributions of source code must retain the above copyright
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#   notice, this list of conditions and the following disclaimer.
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# - Redistributions in binary form must reproduce the above copyright
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#   notice, this list of conditions and the following disclaimer in the
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#   documentation and/or other materials provided with the distribution.
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# - The name of the author may not be used to endorse or promote products
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#   derived from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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326 palkovsky 29
#include <arch/asm/regname.h>
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1 jermar 31
.text
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.macro cp0_read reg
50 jermar 34
	mfc0 $2,\reg
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	j $31
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	nop
1 jermar 37
.endm
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.macro cp0_write reg
50 jermar 40
	mtc0 $4,\reg
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	j $31
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	nop
1 jermar 43
.endm
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.set noat
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.set noreorder
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.set nomacro
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49
.global cpu_halt
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cpu_halt:
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	j cpu_halt
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	nop
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54
 
59 jermar 55
.global memsetb
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memsetb:
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	j _memsetb
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	nop
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1288 jermar 60
 
205 jermar 61
.global memcpy
1288 jermar 62
.global memcpy_from_uspace
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.global memcpy_to_uspace
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.global memcpy_from_uspace_failover_address
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.global memcpy_to_uspace_failover_address
205 jermar 66
memcpy:
1288 jermar 67
memcpy_from_uspace:
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memcpy_to_uspace:
1615 jermar 69
	addiu	$v0,$a1,3
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	li	$v1,-4			# 0xfffffffffffffffc
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	and	$v0,$v0,$v1
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	beq	$a1,$v0,3f
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	move	$t0,$a0
3425 svoboda 74
	move	$t2,$a0			# save dst
105 jermar 75
 
1615 jermar 76
0:
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	beq	$a2,$zero,2f
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	move	$a3,$zero
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1:
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	addu	$v0,$a1,$a3
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	lbu	$a0,0($v0)
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	addu	$v1,$t0,$a3
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	addiu	$a3,$a3,1
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	bne	$a3,$a2,1b
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	sb	$a0,0($v1)
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2:
89
	jr	$ra
3425 svoboda 90
	move	$v0,$t2
1615 jermar 91
 
92
3:
93
	addiu	$v0,$a0,3
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	and	$v0,$v0,$v1
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	bne	$a0,$v0,0b
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	srl	$t1,$a2,2
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98
	beq	$t1,$zero,5f
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	move	$a3,$zero
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101
	move	$a3,$zero
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	move	$a0,$zero
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4:
104
	addu	$v0,$a1,$a0
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	lw	$v1,0($v0)
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	addiu	$a3,$a3,1
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	addu	$v0,$t0,$a0
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	sw	$v1,0($v0)
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	bne	$a3,$t1,4b
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	addiu	$a0,$a0,4
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5:
113
	andi	$a2,$a2,0x3
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	beq	$a2,$zero,2b
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	nop
116
 
117
	sll	$v0,$a3,2
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	addu	$t1,$v0,$t0
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	move	$a3,$zero
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	addu	$t0,$v0,$a1
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6:
122
	addu	$v0,$t0,$a3
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	lbu	$a0,0($v0)
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	addu	$v1,$t1,$a3
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	addiu	$a3,$a3,1
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	bne	$a3,$a2,6b
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	sb	$a0,0($v1)
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129
	jr	$ra
3425 svoboda 130
	move	$v0,$t2
1615 jermar 131
 
1288 jermar 132
memcpy_from_uspace_failover_address:
133
memcpy_to_uspace_failover_address:
1293 palkovsky 134
	jr	$ra
135
	move	$v0, $zero
1288 jermar 136
 
137
 
138
 
326 palkovsky 139
.macro fpu_gp_save reg ctx
140
	mfc1 $t0,$\reg
141
	sw $t0, \reg*4(\ctx)
142
.endm
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144
.macro fpu_gp_restore reg ctx
145
	lw $t0, \reg*4(\ctx)
146
	mtc1 $t0,$\reg
147
.endm
148
 
149
.macro fpu_ct_save reg ctx
150
	cfc1 $t0,$1
151
	sw $t0, (\reg+32)*4(\ctx)
152
.endm	
153
 
154
.macro fpu_ct_restore reg ctx
155
	lw $t0, (\reg+32)*4(\ctx)
156
	ctc1 $t0,$\reg
157
.endm
158
 
159
 
160
.global fpu_context_save
161
fpu_context_save:
924 palkovsky 162
#ifdef ARCH_HAS_FPU
326 palkovsky 163
	fpu_gp_save 0,$a0
164
	fpu_gp_save 1,$a0
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	fpu_gp_save 2,$a0
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	fpu_gp_save 3,$a0
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	fpu_gp_save 4,$a0
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	fpu_gp_save 5,$a0
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	fpu_gp_save 6,$a0
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	fpu_gp_save 7,$a0
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	fpu_gp_save 8,$a0
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	fpu_gp_save 9,$a0
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	fpu_gp_save 10,$a0
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	fpu_gp_save 11,$a0
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	fpu_gp_save 12,$a0
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	fpu_gp_save 13,$a0
177
	fpu_gp_save 14,$a0
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	fpu_gp_save 15,$a0
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	fpu_gp_save 16,$a0
180
	fpu_gp_save 17,$a0
181
	fpu_gp_save 18,$a0
182
	fpu_gp_save 19,$a0
183
	fpu_gp_save 20,$a0
184
	fpu_gp_save 21,$a0
185
	fpu_gp_save 22,$a0
186
	fpu_gp_save 23,$a0
187
	fpu_gp_save 24,$a0
188
	fpu_gp_save 25,$a0
189
	fpu_gp_save 26,$a0
190
	fpu_gp_save 27,$a0
191
	fpu_gp_save 28,$a0
192
	fpu_gp_save 29,$a0
193
	fpu_gp_save 30,$a0
194
	fpu_gp_save 31,$a0
195
 
196
	fpu_ct_save 1,$a0
197
	fpu_ct_save 2,$a0
198
	fpu_ct_save 3,$a0
199
	fpu_ct_save 4,$a0
200
	fpu_ct_save 5,$a0
201
	fpu_ct_save 6,$a0
202
	fpu_ct_save 7,$a0
203
	fpu_ct_save 8,$a0
204
	fpu_ct_save 9,$a0
205
	fpu_ct_save 10,$a0
206
	fpu_ct_save 11,$a0
207
	fpu_ct_save 12,$a0
208
	fpu_ct_save 13,$a0
209
	fpu_ct_save 14,$a0
210
	fpu_ct_save 15,$a0
211
	fpu_ct_save 16,$a0
212
	fpu_ct_save 17,$a0
213
	fpu_ct_save 18,$a0
214
	fpu_ct_save 19,$a0
215
	fpu_ct_save 20,$a0
216
	fpu_ct_save 21,$a0
217
	fpu_ct_save 22,$a0
218
	fpu_ct_save 23,$a0
219
	fpu_ct_save 24,$a0
220
	fpu_ct_save 25,$a0
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	fpu_ct_save 26,$a0
222
	fpu_ct_save 27,$a0
223
	fpu_ct_save 28,$a0
224
	fpu_ct_save 29,$a0
225
	fpu_ct_save 30,$a0
226
	fpu_ct_save 31,$a0
227
#endif		
228
	j $ra
229
	nop
230
 
231
.global fpu_context_restore
232
fpu_context_restore:
924 palkovsky 233
#ifdef ARCH_HAS_FPU
326 palkovsky 234
	fpu_gp_restore 0,$a0
235
	fpu_gp_restore 1,$a0
236
	fpu_gp_restore 2,$a0
237
	fpu_gp_restore 3,$a0
238
	fpu_gp_restore 4,$a0
239
	fpu_gp_restore 5,$a0
240
	fpu_gp_restore 6,$a0
241
	fpu_gp_restore 7,$a0
242
	fpu_gp_restore 8,$a0
243
	fpu_gp_restore 9,$a0
244
	fpu_gp_restore 10,$a0
245
	fpu_gp_restore 11,$a0
246
	fpu_gp_restore 12,$a0
247
	fpu_gp_restore 13,$a0
248
	fpu_gp_restore 14,$a0
249
	fpu_gp_restore 15,$a0
250
	fpu_gp_restore 16,$a0
251
	fpu_gp_restore 17,$a0
252
	fpu_gp_restore 18,$a0
253
	fpu_gp_restore 19,$a0
254
	fpu_gp_restore 20,$a0
255
	fpu_gp_restore 21,$a0
256
	fpu_gp_restore 22,$a0
257
	fpu_gp_restore 23,$a0
258
	fpu_gp_restore 24,$a0
259
	fpu_gp_restore 25,$a0
260
	fpu_gp_restore 26,$a0
261
	fpu_gp_restore 27,$a0
262
	fpu_gp_restore 28,$a0
263
	fpu_gp_restore 29,$a0
264
	fpu_gp_restore 30,$a0
265
	fpu_gp_restore 31,$a0
266
 
267
	fpu_ct_restore 1,$a0
268
	fpu_ct_restore 2,$a0
269
	fpu_ct_restore 3,$a0
270
	fpu_ct_restore 4,$a0
271
	fpu_ct_restore 5,$a0
272
	fpu_ct_restore 6,$a0
273
	fpu_ct_restore 7,$a0
274
	fpu_ct_restore 8,$a0
275
	fpu_ct_restore 9,$a0
276
	fpu_ct_restore 10,$a0
277
	fpu_ct_restore 11,$a0
278
	fpu_ct_restore 12,$a0
279
	fpu_ct_restore 13,$a0
280
	fpu_ct_restore 14,$a0
281
	fpu_ct_restore 15,$a0
282
	fpu_ct_restore 16,$a0
283
	fpu_ct_restore 17,$a0
284
	fpu_ct_restore 18,$a0
285
	fpu_ct_restore 19,$a0
286
	fpu_ct_restore 20,$a0
287
	fpu_ct_restore 21,$a0
288
	fpu_ct_restore 22,$a0
289
	fpu_ct_restore 23,$a0
290
	fpu_ct_restore 24,$a0
291
	fpu_ct_restore 25,$a0
292
	fpu_ct_restore 26,$a0
293
	fpu_ct_restore 27,$a0
294
	fpu_ct_restore 28,$a0
295
	fpu_ct_restore 29,$a0
296
	fpu_ct_restore 30,$a0
297
	fpu_ct_restore 31,$a0
298
#endif	
299
	j $ra
300
	nop