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| Rev | Author | Line No. | Line |
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| 664 | jermar | 1 | /* |
| 2071 | jermar | 2 | * Copyright (c) 2005 Jakub Jermar |
| 664 | jermar | 3 | * All rights reserved. |
| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 1849 | jermar | 29 | /** @addtogroup sparc64 |
| 1702 | cejka | 30 | * @{ |
| 31 | */ |
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| 32 | /** @file |
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| 33 | */ |
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| 34 | |||
| 664 | jermar | 35 | #include <arch/drivers/tick.h> |
| 36 | #include <arch/interrupt.h> |
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| 2089 | decky | 37 | #include <arch/sparc64.h> |
| 664 | jermar | 38 | #include <arch/asm.h> |
| 39 | #include <arch/register.h> |
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| 1881 | jermar | 40 | #include <arch/cpu.h> |
| 41 | #include <arch/boot/boot.h> |
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| 42 | #include <time/clock.h> |
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| 43 | #include <arch.h> |
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| 664 | jermar | 44 | #include <debug.h> |
| 45 | |||
| 1881 | jermar | 46 | #define TICK_RESTART_TIME 50 /* Worst case estimate. */ |
| 47 | |||
| 3664 | rimsky | 48 | /** Initialize tick and stick interrupt. */ |
| 664 | jermar | 49 | void tick_init(void) |
| 50 | { |
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| 3664 | rimsky | 51 | /* initialize TICK interrupt */ |
| 664 | jermar | 52 | tick_compare_reg_t compare; |
| 53 | interrupt_register(14, "tick_int", tick_interrupt); |
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| 54 | compare.int_dis = false; |
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| 2044 | jermar | 55 | compare.tick_cmpr = CPU->arch.clock_frequency / HZ; |
| 56 | CPU->arch.next_tick_cmpr = compare.tick_cmpr; |
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| 664 | jermar | 57 | tick_compare_write(compare.value); |
| 58 | tick_write(0); |
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| 3664 | rimsky | 59 | |
| 60 | #if defined (US3) |
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| 61 | /* disable STICK interrupts and clear any pending ones */ |
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| 62 | tick_compare_reg_t stick_compare; |
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| 63 | softint_reg_t clear; |
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| 64 | |||
| 65 | stick_compare.value = stick_compare_read(); |
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| 66 | stick_compare.int_dis = true; |
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| 67 | stick_compare.tick_cmpr = 0; |
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| 68 | stick_compare_write(stick_compare.value); |
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| 69 | |||
| 70 | clear.value = 0; |
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| 71 | clear.stick_int = 1; |
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| 72 | clear_softint_write(clear.value); |
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| 73 | #endif |
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| 664 | jermar | 74 | } |
| 75 | |||
| 665 | jermar | 76 | /** Process tick interrupt. |
| 77 | * |
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| 78 | * @param n Interrupt Level, 14, (can be ignored) |
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| 958 | jermar | 79 | * @param istate Interrupted state. |
| 665 | jermar | 80 | */ |
| 958 | jermar | 81 | void tick_interrupt(int n, istate_t *istate) |
| 664 | jermar | 82 | { |
| 3664 | rimsky | 83 | |
| 665 | jermar | 84 | softint_reg_t softint, clear; |
| 2044 | jermar | 85 | uint64_t drift; |
| 3664 | rimsky | 86 | |
| 665 | jermar | 87 | softint.value = softint_read(); |
| 88 | |||
| 89 | /* |
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| 90 | * Make sure we are servicing interrupt_level_14 |
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| 91 | */ |
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| 92 | ASSERT(n == 14); |
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| 93 | |||
| 94 | /* |
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| 95 | * Make sure we are servicing TICK_INT. |
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| 96 | */ |
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| 97 | ASSERT(softint.tick_int); |
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| 98 | |||
| 99 | /* |
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| 100 | * Clear tick interrupt. |
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| 101 | */ |
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| 102 | clear.value = 0; |
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| 103 | clear.tick_int = 1; |
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| 104 | clear_softint_write(clear.value); |
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| 105 | |||
| 106 | /* |
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| 2044 | jermar | 107 | * Reprogram the compare register. |
| 108 | * For now, we can ignore the potential of the registers to overflow. |
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| 109 | * On a 360MHz Ultra 60, the 63-bit compare counter will overflow in |
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| 110 | * about 812 years. If there was a 2GHz UltraSPARC computer, it would |
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| 111 | * overflow only in 146 years. |
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| 665 | jermar | 112 | */ |
| 2044 | jermar | 113 | drift = tick_read() - CPU->arch.next_tick_cmpr; |
| 114 | while (drift > CPU->arch.clock_frequency / HZ) { |
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| 115 | drift -= CPU->arch.clock_frequency / HZ; |
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| 1881 | jermar | 116 | CPU->missed_clock_ticks++; |
| 117 | } |
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| 2107 | jermar | 118 | CPU->arch.next_tick_cmpr = tick_read() + |
| 119 | (CPU->arch.clock_frequency / HZ) - drift; |
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| 2044 | jermar | 120 | tick_compare_write(CPU->arch.next_tick_cmpr); |
| 665 | jermar | 121 | clock(); |
| 664 | jermar | 122 | } |
| 1702 | cejka | 123 | |
| 1849 | jermar | 124 | /** @} |
| 1702 | cejka | 125 | */ |