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418 | jermar | 1 | /* |
2071 | jermar | 2 | * Copyright (c) 2005 Jakub Jermar |
418 | jermar | 3 | * All rights reserved. |
4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
1822 | jermar | 29 | /** @addtogroup sparc64mm |
1702 | cejka | 30 | * @{ |
31 | */ |
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32 | /** @file |
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33 | */ |
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34 | |||
1860 | jermar | 35 | #ifndef KERN_sparc64_TLB_H_ |
36 | #define KERN_sparc64_TLB_H_ |
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418 | jermar | 37 | |
3450 | rimsky | 38 | #if defined (US) |
569 | jermar | 39 | #define ITLB_ENTRY_COUNT 64 |
40 | #define DTLB_ENTRY_COUNT 64 |
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3450 | rimsky | 41 | #define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT |
42 | #endif |
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569 | jermar | 43 | |
3591 | rimsky | 44 | /** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */ |
3450 | rimsky | 45 | #if defined (US3) |
46 | #define DTLB_MAX_LOCKED_ENTRIES 16 |
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47 | #endif |
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48 | |||
1823 | jermar | 49 | #define MEM_CONTEXT_KERNEL 0 |
50 | #define MEM_CONTEXT_TEMP 1 |
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51 | |||
619 | jermar | 52 | /** Page sizes. */ |
53 | #define PAGESIZE_8K 0 |
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54 | #define PAGESIZE_64K 1 |
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55 | #define PAGESIZE_512K 2 |
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56 | #define PAGESIZE_4M 3 |
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531 | jermar | 57 | |
901 | jermar | 58 | /** Bit width of the TLB-locked portion of kernel address space. */ |
59 | #define KERNEL_PAGE_WIDTH 22 /* 4M */ |
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60 | |||
1823 | jermar | 61 | /* TLB Demap Operation types. */ |
62 | #define TLB_DEMAP_PAGE 0 |
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63 | #define TLB_DEMAP_CONTEXT 1 |
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3450 | rimsky | 64 | #if defined (US3) |
65 | #define TLB_DEMAP_ALL 2 |
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66 | #endif |
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1823 | jermar | 67 | |
68 | #define TLB_DEMAP_TYPE_SHIFT 6 |
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69 | |||
70 | /* TLB Demap Operation Context register encodings. */ |
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71 | #define TLB_DEMAP_PRIMARY 0 |
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72 | #define TLB_DEMAP_SECONDARY 1 |
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73 | #define TLB_DEMAP_NUCLEUS 2 |
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74 | |||
3450 | rimsky | 75 | /* There are more TLBs in one MMU in US3, their codes are defined here. */ |
3440 | rimsky | 76 | #if defined (US3) |
3591 | rimsky | 77 | /* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */ |
78 | #define TLB_DSMALL 0 |
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79 | #define TLB_DBIG_0 2 |
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80 | #define TLB_DBIG_1 3 |
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3440 | rimsky | 81 | |
3591 | rimsky | 82 | /* I-MMU: one small (16-entry) TLB and one big TLB */ |
83 | #define TLB_ISMALL 0 |
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84 | #define TLB_IBIG 2 |
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3440 | rimsky | 85 | #endif |
86 | |||
1823 | jermar | 87 | #define TLB_DEMAP_CONTEXT_SHIFT 4 |
88 | |||
89 | /* TLB Tag Access shifts */ |
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90 | #define TLB_TAG_ACCESS_CONTEXT_SHIFT 0 |
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2054 | jermar | 91 | #define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1) |
1823 | jermar | 92 | #define TLB_TAG_ACCESS_VPN_SHIFT 13 |
93 | |||
94 | #ifndef __ASM__ |
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95 | |||
96 | #include <arch/mm/tte.h> |
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97 | #include <arch/mm/mmu.h> |
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98 | #include <arch/mm/page.h> |
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99 | #include <arch/asm.h> |
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100 | #include <arch/barrier.h> |
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101 | #include <arch/types.h> |
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3591 | rimsky | 102 | #include <arch/register.h> |
103 | #include <arch/cpu.h> |
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1823 | jermar | 104 | |
873 | jermar | 105 | union tlb_context_reg { |
1780 | jermar | 106 | uint64_t v; |
873 | jermar | 107 | struct { |
108 | unsigned long : 51; |
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109 | unsigned context : 13; /**< Context/ASID. */ |
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110 | } __attribute__ ((packed)); |
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111 | }; |
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112 | typedef union tlb_context_reg tlb_context_reg_t; |
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113 | |||
530 | jermar | 114 | /** I-/D-TLB Data In/Access Register type. */ |
115 | typedef tte_data_t tlb_data_t; |
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116 | |||
569 | jermar | 117 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
3440 | rimsky | 118 | |
119 | #if defined (US) |
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120 | |||
569 | jermar | 121 | union tlb_data_access_addr { |
1780 | jermar | 122 | uint64_t value; |
569 | jermar | 123 | struct { |
1780 | jermar | 124 | uint64_t : 55; |
569 | jermar | 125 | unsigned tlb_entry : 6; |
126 | unsigned : 3; |
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127 | } __attribute__ ((packed)); |
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128 | }; |
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3440 | rimsky | 129 | typedef union tlb_data_access_addr dtlb_data_access_addr_t; |
130 | typedef union tlb_data_access_addr dtlb_tag_read_addr_t; |
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131 | typedef union tlb_data_access_addr itlb_data_access_addr_t; |
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132 | typedef union tlb_data_access_addr itlb_tag_read_addr_t; |
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418 | jermar | 133 | |
3440 | rimsky | 134 | #elif defined (US3) |
135 | |||
136 | /* |
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137 | * In US3, I-MMU and D-MMU have different formats of the data |
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138 | * access register virtual address. In the corresponding |
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139 | * structures the member variable for the entry number is |
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140 | * called "local_tlb_entry" - it contrast with the "tlb_entry" |
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141 | * for the US data access register VA structure. The rationale |
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142 | * behind this is to prevent careless mistakes in the code |
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143 | * caused by setting only the entry number and not the TLB |
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144 | * number in the US3 code (when taking the code from US). |
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145 | */ |
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146 | |||
147 | union dtlb_data_access_addr { |
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148 | uint64_t value; |
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149 | struct { |
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150 | uint64_t : 45; |
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151 | unsigned : 1; |
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152 | unsigned tlb_number : 2; |
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153 | unsigned : 4; |
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154 | unsigned local_tlb_entry : 9; |
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155 | unsigned : 3; |
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156 | } __attribute__ ((packed)); |
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157 | }; |
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158 | typedef union dtlb_data_access_addr dtlb_data_access_addr_t; |
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159 | typedef union dtlb_data_access_addr dtlb_tag_read_addr_t; |
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160 | |||
161 | union itlb_data_access_addr { |
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162 | uint64_t value; |
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163 | struct { |
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164 | uint64_t : 45; |
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165 | unsigned : 1; |
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166 | unsigned tlb_number : 2; |
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167 | unsigned : 6; |
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168 | unsigned local_tlb_entry : 7; |
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169 | unsigned : 3; |
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170 | } __attribute__ ((packed)); |
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171 | }; |
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172 | typedef union itlb_data_access_addr itlb_data_access_addr_t; |
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173 | typedef union itlb_data_access_addr itlb_tag_read_addr_t; |
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174 | |||
175 | #endif |
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176 | |||
569 | jermar | 177 | /** I-/D-TLB Tag Read Register. */ |
178 | union tlb_tag_read_reg { |
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1780 | jermar | 179 | uint64_t value; |
569 | jermar | 180 | struct { |
2054 | jermar | 181 | uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ |
182 | unsigned context : 13; /**< Context identifier. */ |
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569 | jermar | 183 | } __attribute__ ((packed)); |
184 | }; |
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185 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
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613 | jermar | 186 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
569 | jermar | 187 | |
617 | jermar | 188 | |
189 | /** TLB Demap Operation Address. */ |
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190 | union tlb_demap_addr { |
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1780 | jermar | 191 | uint64_t value; |
617 | jermar | 192 | struct { |
1851 | jermar | 193 | uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ |
3450 | rimsky | 194 | #if defined (US) |
617 | jermar | 195 | unsigned : 6; /**< Ignored. */ |
196 | unsigned type : 1; /**< The type of demap operation. */ |
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3450 | rimsky | 197 | #elif defined (US3) |
198 | unsigned : 5; /**< Ignored. */ |
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199 | unsigned type: 2; /**< The type of demap operation. */ |
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200 | #endif |
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617 | jermar | 201 | unsigned context : 2; /**< Context register selection. */ |
202 | unsigned : 4; /**< Zero. */ |
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203 | } __attribute__ ((packed)); |
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204 | }; |
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205 | typedef union tlb_demap_addr tlb_demap_addr_t; |
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206 | |||
873 | jermar | 207 | /** TLB Synchronous Fault Status Register. */ |
208 | union tlb_sfsr_reg { |
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1780 | jermar | 209 | uint64_t value; |
873 | jermar | 210 | struct { |
3450 | rimsky | 211 | #if defined (US) |
1851 | jermar | 212 | unsigned long : 40; /**< Implementation dependent. */ |
873 | jermar | 213 | unsigned asi : 8; /**< ASI. */ |
1851 | jermar | 214 | unsigned : 2; |
877 | jermar | 215 | unsigned ft : 7; /**< Fault type. */ |
3450 | rimsky | 216 | #elif defined (US3) |
217 | unsigned long : 39; /**< Implementation dependent. */ |
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218 | unsigned nf : 1; /**< Non-faulting load. */ |
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219 | unsigned asi : 8; /**< ASI. */ |
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220 | unsigned tm : 1; /**< I-TLB miss. */ |
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221 | unsigned : 3; /**< Reserved. */ |
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222 | unsigned ft : 5; /**< Fault type. */ |
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223 | #endif |
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873 | jermar | 224 | unsigned e : 1; /**< Side-effect bit. */ |
225 | unsigned ct : 2; /**< Context Register selection. */ |
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226 | unsigned pr : 1; /**< Privilege bit. */ |
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227 | unsigned w : 1; /**< Write bit. */ |
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228 | unsigned ow : 1; /**< Overwrite bit. */ |
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877 | jermar | 229 | unsigned fv : 1; /**< Fault Valid bit. */ |
873 | jermar | 230 | } __attribute__ ((packed)); |
231 | }; |
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232 | typedef union tlb_sfsr_reg tlb_sfsr_reg_t; |
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233 | |||
3591 | rimsky | 234 | #if defined (US3) |
235 | |||
236 | /* |
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237 | * Functions for determining the number of entries in TLBs. They either return |
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238 | * a constant value or a value based on the CPU autodetection. |
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239 | */ |
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240 | |||
241 | /** |
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242 | * Determine the number od entries in the DMMU's small TLB. |
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243 | */ |
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244 | static inline uint16_t tlb_dsmall_size(void) |
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245 | { |
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246 | return 16; |
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247 | } |
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248 | |||
249 | /** |
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250 | * Determine the number od entries in each DMMU's big TLB. |
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251 | */ |
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252 | static inline uint16_t tlb_dbig_size(void) |
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253 | { |
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254 | return 512; |
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255 | } |
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256 | |||
257 | /** |
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258 | * Determine the number od entries in the IMMU's small TLB. |
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259 | */ |
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260 | static inline uint16_t tlb_ismall_size(void) |
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261 | { |
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262 | return 16; |
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263 | } |
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264 | |||
265 | /** |
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266 | * Determine the number od entries in the IMMU's big TLB. |
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267 | */ |
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268 | static inline uint16_t tlb_ibig_size(void) |
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269 | { |
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270 | if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS) |
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271 | return 512; |
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272 | else |
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273 | return 128; |
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274 | } |
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275 | |||
276 | #endif |
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277 | |||
873 | jermar | 278 | /** Read MMU Primary Context Register. |
279 | * |
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280 | * @return Current value of Primary Context Register. |
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281 | */ |
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1780 | jermar | 282 | static inline uint64_t mmu_primary_context_read(void) |
873 | jermar | 283 | { |
284 | return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); |
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285 | } |
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286 | |||
287 | /** Write MMU Primary Context Register. |
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288 | * |
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289 | * @param v New value of Primary Context Register. |
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290 | */ |
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1780 | jermar | 291 | static inline void mmu_primary_context_write(uint64_t v) |
873 | jermar | 292 | { |
293 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
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3145 | jermar | 294 | flush_pipeline(); |
873 | jermar | 295 | } |
296 | |||
297 | /** Read MMU Secondary Context Register. |
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298 | * |
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299 | * @return Current value of Secondary Context Register. |
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300 | */ |
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1780 | jermar | 301 | static inline uint64_t mmu_secondary_context_read(void) |
873 | jermar | 302 | { |
303 | return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); |
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304 | } |
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305 | |||
306 | /** Write MMU Primary Context Register. |
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307 | * |
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308 | * @param v New value of Primary Context Register. |
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309 | */ |
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1780 | jermar | 310 | static inline void mmu_secondary_context_write(uint64_t v) |
873 | jermar | 311 | { |
1864 | jermar | 312 | asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v); |
3145 | jermar | 313 | flush_pipeline(); |
873 | jermar | 314 | } |
315 | |||
3440 | rimsky | 316 | #if defined (US) |
317 | |||
569 | jermar | 318 | /** Read IMMU TLB Data Access Register. |
319 | * |
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320 | * @param entry TLB Entry index. |
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321 | * |
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322 | * @return Current value of specified IMMU TLB Data Access Register. |
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323 | */ |
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1780 | jermar | 324 | static inline uint64_t itlb_data_access_read(index_t entry) |
569 | jermar | 325 | { |
3440 | rimsky | 326 | itlb_data_access_addr_t reg; |
569 | jermar | 327 | |
328 | reg.value = 0; |
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329 | reg.tlb_entry = entry; |
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330 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
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331 | } |
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332 | |||
617 | jermar | 333 | /** Write IMMU TLB Data Access Register. |
334 | * |
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335 | * @param entry TLB Entry index. |
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336 | * @param value Value to be written. |
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337 | */ |
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1780 | jermar | 338 | static inline void itlb_data_access_write(index_t entry, uint64_t value) |
617 | jermar | 339 | { |
3440 | rimsky | 340 | itlb_data_access_addr_t reg; |
617 | jermar | 341 | |
342 | reg.value = 0; |
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343 | reg.tlb_entry = entry; |
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344 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
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3145 | jermar | 345 | flush_pipeline(); |
617 | jermar | 346 | } |
347 | |||
569 | jermar | 348 | /** Read DMMU TLB Data Access Register. |
349 | * |
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350 | * @param entry TLB Entry index. |
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351 | * |
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352 | * @return Current value of specified DMMU TLB Data Access Register. |
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353 | */ |
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1780 | jermar | 354 | static inline uint64_t dtlb_data_access_read(index_t entry) |
569 | jermar | 355 | { |
3440 | rimsky | 356 | dtlb_data_access_addr_t reg; |
569 | jermar | 357 | |
358 | reg.value = 0; |
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359 | reg.tlb_entry = entry; |
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360 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
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361 | } |
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362 | |||
617 | jermar | 363 | /** Write DMMU TLB Data Access Register. |
364 | * |
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365 | * @param entry TLB Entry index. |
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366 | * @param value Value to be written. |
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367 | */ |
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1780 | jermar | 368 | static inline void dtlb_data_access_write(index_t entry, uint64_t value) |
617 | jermar | 369 | { |
3440 | rimsky | 370 | dtlb_data_access_addr_t reg; |
617 | jermar | 371 | |
372 | reg.value = 0; |
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373 | reg.tlb_entry = entry; |
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374 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
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1822 | jermar | 375 | membar(); |
617 | jermar | 376 | } |
377 | |||
569 | jermar | 378 | /** Read IMMU TLB Tag Read Register. |
379 | * |
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380 | * @param entry TLB Entry index. |
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381 | * |
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382 | * @return Current value of specified IMMU TLB Tag Read Register. |
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383 | */ |
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1780 | jermar | 384 | static inline uint64_t itlb_tag_read_read(index_t entry) |
569 | jermar | 385 | { |
3440 | rimsky | 386 | itlb_tag_read_addr_t tag; |
569 | jermar | 387 | |
388 | tag.value = 0; |
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389 | tag.tlb_entry = entry; |
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390 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
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391 | } |
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392 | |||
393 | /** Read DMMU TLB Tag Read Register. |
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394 | * |
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395 | * @param entry TLB Entry index. |
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396 | * |
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397 | * @return Current value of specified DMMU TLB Tag Read Register. |
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398 | */ |
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1780 | jermar | 399 | static inline uint64_t dtlb_tag_read_read(index_t entry) |
569 | jermar | 400 | { |
3440 | rimsky | 401 | dtlb_tag_read_addr_t tag; |
569 | jermar | 402 | |
403 | tag.value = 0; |
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404 | tag.tlb_entry = entry; |
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405 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
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406 | } |
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407 | |||
3440 | rimsky | 408 | #elif defined (US3) |
409 | |||
410 | |||
411 | /** Read IMMU TLB Data Access Register. |
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412 | * |
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3591 | rimsky | 413 | * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) |
3440 | rimsky | 414 | * @param entry TLB Entry index. |
415 | * |
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416 | * @return Current value of specified IMMU TLB Data Access Register. |
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417 | */ |
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418 | static inline uint64_t itlb_data_access_read(int tlb, index_t entry) |
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419 | { |
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420 | itlb_data_access_addr_t reg; |
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421 | |||
422 | reg.value = 0; |
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423 | reg.tlb_number = tlb; |
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424 | reg.local_tlb_entry = entry; |
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425 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
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426 | } |
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427 | |||
428 | /** Write IMMU TLB Data Access Register. |
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3591 | rimsky | 429 | * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) |
3440 | rimsky | 430 | * @param entry TLB Entry index. |
431 | * @param value Value to be written. |
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432 | */ |
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3618 | rimsky | 433 | static inline void itlb_data_access_write(int tlb, index_t entry, |
434 | uint64_t value) |
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3440 | rimsky | 435 | { |
436 | itlb_data_access_addr_t reg; |
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437 | |||
438 | reg.value = 0; |
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439 | reg.tlb_number = tlb; |
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440 | reg.local_tlb_entry = entry; |
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441 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
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442 | flush_pipeline(); |
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443 | } |
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444 | |||
445 | /** Read DMMU TLB Data Access Register. |
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446 | * |
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3591 | rimsky | 447 | * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG) |
3440 | rimsky | 448 | * @param entry TLB Entry index. |
449 | * |
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450 | * @return Current value of specified DMMU TLB Data Access Register. |
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451 | */ |
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452 | static inline uint64_t dtlb_data_access_read(int tlb, index_t entry) |
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453 | { |
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454 | dtlb_data_access_addr_t reg; |
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455 | |||
456 | reg.value = 0; |
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457 | reg.tlb_number = tlb; |
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458 | reg.local_tlb_entry = entry; |
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459 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
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460 | } |
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461 | |||
462 | /** Write DMMU TLB Data Access Register. |
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463 | * |
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3591 | rimsky | 464 | * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1) |
3440 | rimsky | 465 | * @param entry TLB Entry index. |
466 | * @param value Value to be written. |
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467 | */ |
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3618 | rimsky | 468 | static inline void dtlb_data_access_write(int tlb, index_t entry, |
469 | uint64_t value) |
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3440 | rimsky | 470 | { |
471 | dtlb_data_access_addr_t reg; |
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472 | |||
473 | reg.value = 0; |
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474 | reg.tlb_number = tlb; |
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475 | reg.local_tlb_entry = entry; |
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476 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
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477 | membar(); |
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478 | } |
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479 | |||
480 | /** Read IMMU TLB Tag Read Register. |
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481 | * |
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3591 | rimsky | 482 | * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) |
3440 | rimsky | 483 | * @param entry TLB Entry index. |
484 | * |
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485 | * @return Current value of specified IMMU TLB Tag Read Register. |
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486 | */ |
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487 | static inline uint64_t itlb_tag_read_read(int tlb, index_t entry) |
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488 | { |
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489 | itlb_tag_read_addr_t tag; |
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490 | |||
491 | tag.value = 0; |
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492 | tag.tlb_number = tlb; |
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493 | tag.local_tlb_entry = entry; |
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494 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
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495 | } |
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496 | |||
497 | /** Read DMMU TLB Tag Read Register. |
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498 | * |
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3591 | rimsky | 499 | * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1) |
3440 | rimsky | 500 | * @param entry TLB Entry index. |
501 | * |
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502 | * @return Current value of specified DMMU TLB Tag Read Register. |
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503 | */ |
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504 | static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry) |
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505 | { |
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506 | dtlb_tag_read_addr_t tag; |
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507 | |||
508 | tag.value = 0; |
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509 | tag.tlb_number = tlb; |
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510 | tag.local_tlb_entry = entry; |
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511 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
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512 | } |
||
513 | |||
514 | #endif |
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515 | |||
516 | |||
613 | jermar | 517 | /** Write IMMU TLB Tag Access Register. |
518 | * |
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519 | * @param v Value to be written. |
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520 | */ |
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1780 | jermar | 521 | static inline void itlb_tag_access_write(uint64_t v) |
613 | jermar | 522 | { |
523 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
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3145 | jermar | 524 | flush_pipeline(); |
613 | jermar | 525 | } |
526 | |||
877 | jermar | 527 | /** Read IMMU TLB Tag Access Register. |
528 | * |
||
529 | * @return Current value of IMMU TLB Tag Access Register. |
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530 | */ |
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1780 | jermar | 531 | static inline uint64_t itlb_tag_access_read(void) |
877 | jermar | 532 | { |
533 | return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); |
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534 | } |
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535 | |||
613 | jermar | 536 | /** Write DMMU TLB Tag Access Register. |
537 | * |
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538 | * @param v Value to be written. |
||
539 | */ |
||
1780 | jermar | 540 | static inline void dtlb_tag_access_write(uint64_t v) |
613 | jermar | 541 | { |
542 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
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1822 | jermar | 543 | membar(); |
613 | jermar | 544 | } |
545 | |||
877 | jermar | 546 | /** Read DMMU TLB Tag Access Register. |
547 | * |
||
548 | * @return Current value of DMMU TLB Tag Access Register. |
||
549 | */ |
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1780 | jermar | 550 | static inline uint64_t dtlb_tag_access_read(void) |
877 | jermar | 551 | { |
552 | return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); |
||
553 | } |
||
554 | |||
555 | |||
613 | jermar | 556 | /** Write IMMU TLB Data in Register. |
557 | * |
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558 | * @param v Value to be written. |
||
559 | */ |
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1780 | jermar | 560 | static inline void itlb_data_in_write(uint64_t v) |
613 | jermar | 561 | { |
562 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
||
3145 | jermar | 563 | flush_pipeline(); |
613 | jermar | 564 | } |
565 | |||
566 | /** Write DMMU TLB Data in Register. |
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567 | * |
||
568 | * @param v Value to be written. |
||
569 | */ |
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1780 | jermar | 570 | static inline void dtlb_data_in_write(uint64_t v) |
613 | jermar | 571 | { |
572 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
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1822 | jermar | 573 | membar(); |
613 | jermar | 574 | } |
575 | |||
873 | jermar | 576 | /** Read ITLB Synchronous Fault Status Register. |
577 | * |
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578 | * @return Current content of I-SFSR register. |
||
579 | */ |
||
1780 | jermar | 580 | static inline uint64_t itlb_sfsr_read(void) |
873 | jermar | 581 | { |
582 | return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); |
||
583 | } |
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584 | |||
585 | /** Write ITLB Synchronous Fault Status Register. |
||
586 | * |
||
587 | * @param v New value of I-SFSR register. |
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588 | */ |
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1780 | jermar | 589 | static inline void itlb_sfsr_write(uint64_t v) |
873 | jermar | 590 | { |
591 | asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); |
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3145 | jermar | 592 | flush_pipeline(); |
873 | jermar | 593 | } |
594 | |||
595 | /** Read DTLB Synchronous Fault Status Register. |
||
596 | * |
||
597 | * @return Current content of D-SFSR register. |
||
598 | */ |
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1780 | jermar | 599 | static inline uint64_t dtlb_sfsr_read(void) |
873 | jermar | 600 | { |
601 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); |
||
602 | } |
||
603 | |||
604 | /** Write DTLB Synchronous Fault Status Register. |
||
605 | * |
||
606 | * @param v New value of D-SFSR register. |
||
607 | */ |
||
1780 | jermar | 608 | static inline void dtlb_sfsr_write(uint64_t v) |
873 | jermar | 609 | { |
610 | asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); |
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1822 | jermar | 611 | membar(); |
873 | jermar | 612 | } |
613 | |||
614 | /** Read DTLB Synchronous Fault Address Register. |
||
615 | * |
||
616 | * @return Current content of D-SFAR register. |
||
617 | */ |
||
1780 | jermar | 618 | static inline uint64_t dtlb_sfar_read(void) |
873 | jermar | 619 | { |
620 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
||
621 | } |
||
622 | |||
617 | jermar | 623 | /** Perform IMMU TLB Demap Operation. |
624 | * |
||
3450 | rimsky | 625 | * @param type |
626 | * Selects between context and page demap |
||
3607 | rimsky | 627 | * (and entire MMU demap on US3). |
2054 | jermar | 628 | * @param context_encoding Specifies which Context register has Context ID for |
629 | * demap. |
||
617 | jermar | 630 | * @param page Address which is on the page to be demapped. |
631 | */ |
||
1780 | jermar | 632 | static inline void itlb_demap(int type, int context_encoding, uintptr_t page) |
617 | jermar | 633 | { |
634 | tlb_demap_addr_t da; |
||
635 | page_address_t pg; |
||
636 | |||
637 | da.value = 0; |
||
638 | pg.address = page; |
||
639 | |||
640 | da.type = type; |
||
641 | da.context = context_encoding; |
||
642 | da.vpn = pg.vpn; |
||
643 | |||
2054 | jermar | 644 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the |
645 | * address within the |
||
646 | * ASI */ |
||
3145 | jermar | 647 | flush_pipeline(); |
617 | jermar | 648 | } |
649 | |||
650 | /** Perform DMMU TLB Demap Operation. |
||
651 | * |
||
3450 | rimsky | 652 | * @param type |
653 | * Selects between context and page demap |
||
3607 | rimsky | 654 | * (and entire MMU demap on US3). |
2054 | jermar | 655 | * @param context_encoding Specifies which Context register has Context ID for |
656 | * demap. |
||
617 | jermar | 657 | * @param page Address which is on the page to be demapped. |
658 | */ |
||
1780 | jermar | 659 | static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) |
617 | jermar | 660 | { |
661 | tlb_demap_addr_t da; |
||
662 | page_address_t pg; |
||
663 | |||
664 | da.value = 0; |
||
665 | pg.address = page; |
||
666 | |||
667 | da.type = type; |
||
668 | da.context = context_encoding; |
||
669 | da.vpn = pg.vpn; |
||
670 | |||
2054 | jermar | 671 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the |
672 | * address within the |
||
673 | * ASI */ |
||
1822 | jermar | 674 | membar(); |
617 | jermar | 675 | } |
676 | |||
2231 | jermar | 677 | extern void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate); |
678 | extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate); |
||
679 | extern void fast_data_access_protection(tlb_tag_access_reg_t tag , istate_t *istate); |
||
863 | jermar | 680 | |
1780 | jermar | 681 | extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable); |
897 | jermar | 682 | |
1946 | jermar | 683 | extern void dump_sfsr_and_sfar(void); |
684 | |||
1823 | jermar | 685 | #endif /* !def __ASM__ */ |
686 | |||
418 | jermar | 687 | #endif |
1702 | cejka | 688 | |
1822 | jermar | 689 | /** @} |
3493 | rimsky | 690 | */ |