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418 | jermar | 1 | /* |
2071 | jermar | 2 | * Copyright (c) 2005 Jakub Jermar |
418 | jermar | 3 | * All rights reserved. |
4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
1822 | jermar | 29 | /** @addtogroup sparc64mm |
1702 | cejka | 30 | * @{ |
31 | */ |
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32 | /** @file |
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33 | */ |
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34 | |||
1860 | jermar | 35 | #ifndef KERN_sparc64_TLB_H_ |
36 | #define KERN_sparc64_TLB_H_ |
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418 | jermar | 37 | |
569 | jermar | 38 | #define ITLB_ENTRY_COUNT 64 |
39 | #define DTLB_ENTRY_COUNT 64 |
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40 | |||
1823 | jermar | 41 | #define MEM_CONTEXT_KERNEL 0 |
42 | #define MEM_CONTEXT_TEMP 1 |
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43 | |||
619 | jermar | 44 | /** Page sizes. */ |
45 | #define PAGESIZE_8K 0 |
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46 | #define PAGESIZE_64K 1 |
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47 | #define PAGESIZE_512K 2 |
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48 | #define PAGESIZE_4M 3 |
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531 | jermar | 49 | |
901 | jermar | 50 | /** Bit width of the TLB-locked portion of kernel address space. */ |
51 | #define KERNEL_PAGE_WIDTH 22 /* 4M */ |
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52 | |||
1823 | jermar | 53 | /* TLB Demap Operation types. */ |
54 | #define TLB_DEMAP_PAGE 0 |
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55 | #define TLB_DEMAP_CONTEXT 1 |
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56 | |||
57 | #define TLB_DEMAP_TYPE_SHIFT 6 |
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58 | |||
59 | /* TLB Demap Operation Context register encodings. */ |
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60 | #define TLB_DEMAP_PRIMARY 0 |
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61 | #define TLB_DEMAP_SECONDARY 1 |
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62 | #define TLB_DEMAP_NUCLEUS 2 |
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63 | |||
3440 | rimsky | 64 | /* there are more TLBs in one MMU in US3, their codes are defined here */ |
65 | #if defined (US3) |
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66 | /* D-MMU: one 16-entry TLB and two 512-entry TLBs */ |
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67 | #define TLB_DT16 0 |
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68 | #define TLB_DT512_1 2 |
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69 | #define TLB_DT512_2 3 |
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70 | |||
71 | /* I-MMU: one 16-entry TLB and one 128-entry TLB */ |
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72 | #define TLB_IT16 0 |
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73 | #define TLB_IT128 2 |
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74 | #endif |
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75 | |||
1823 | jermar | 76 | #define TLB_DEMAP_CONTEXT_SHIFT 4 |
77 | |||
78 | /* TLB Tag Access shifts */ |
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79 | #define TLB_TAG_ACCESS_CONTEXT_SHIFT 0 |
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2054 | jermar | 80 | #define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1) |
1823 | jermar | 81 | #define TLB_TAG_ACCESS_VPN_SHIFT 13 |
82 | |||
83 | #ifndef __ASM__ |
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84 | |||
85 | #include <arch/mm/tte.h> |
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86 | #include <arch/mm/mmu.h> |
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87 | #include <arch/mm/page.h> |
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88 | #include <arch/asm.h> |
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89 | #include <arch/barrier.h> |
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90 | #include <arch/types.h> |
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91 | |||
873 | jermar | 92 | union tlb_context_reg { |
1780 | jermar | 93 | uint64_t v; |
873 | jermar | 94 | struct { |
95 | unsigned long : 51; |
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96 | unsigned context : 13; /**< Context/ASID. */ |
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97 | } __attribute__ ((packed)); |
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98 | }; |
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99 | typedef union tlb_context_reg tlb_context_reg_t; |
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100 | |||
530 | jermar | 101 | /** I-/D-TLB Data In/Access Register type. */ |
102 | typedef tte_data_t tlb_data_t; |
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103 | |||
569 | jermar | 104 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
3440 | rimsky | 105 | |
106 | #if defined (US) |
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107 | |||
569 | jermar | 108 | union tlb_data_access_addr { |
1780 | jermar | 109 | uint64_t value; |
569 | jermar | 110 | struct { |
1780 | jermar | 111 | uint64_t : 55; |
569 | jermar | 112 | unsigned tlb_entry : 6; |
113 | unsigned : 3; |
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114 | } __attribute__ ((packed)); |
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115 | }; |
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3440 | rimsky | 116 | typedef union tlb_data_access_addr dtlb_data_access_addr_t; |
117 | typedef union tlb_data_access_addr dtlb_tag_read_addr_t; |
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118 | typedef union tlb_data_access_addr itlb_data_access_addr_t; |
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119 | typedef union tlb_data_access_addr itlb_tag_read_addr_t; |
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418 | jermar | 120 | |
3440 | rimsky | 121 | #elif defined (US3) |
122 | |||
123 | /* |
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124 | * In US3, I-MMU and D-MMU have different formats of the data |
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125 | * access register virtual address. In the corresponding |
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126 | * structures the member variable for the entry number is |
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127 | * called "local_tlb_entry" - it contrast with the "tlb_entry" |
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128 | * for the US data access register VA structure. The rationale |
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129 | * behind this is to prevent careless mistakes in the code |
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130 | * caused by setting only the entry number and not the TLB |
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131 | * number in the US3 code (when taking the code from US). |
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132 | */ |
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133 | |||
134 | union dtlb_data_access_addr { |
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135 | uint64_t value; |
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136 | struct { |
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137 | uint64_t : 45; |
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138 | unsigned : 1; |
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139 | unsigned tlb_number : 2; |
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140 | unsigned : 4; |
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141 | unsigned local_tlb_entry : 9; |
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142 | unsigned : 3; |
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143 | } __attribute__ ((packed)); |
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144 | }; |
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145 | typedef union dtlb_data_access_addr dtlb_data_access_addr_t; |
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146 | typedef union dtlb_data_access_addr dtlb_tag_read_addr_t; |
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147 | |||
148 | union itlb_data_access_addr { |
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149 | uint64_t value; |
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150 | struct { |
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151 | uint64_t : 45; |
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152 | unsigned : 1; |
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153 | unsigned tlb_number : 2; |
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154 | unsigned : 6; |
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155 | unsigned local_tlb_entry : 7; |
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156 | unsigned : 3; |
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157 | } __attribute__ ((packed)); |
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158 | }; |
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159 | typedef union itlb_data_access_addr itlb_data_access_addr_t; |
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160 | typedef union itlb_data_access_addr itlb_tag_read_addr_t; |
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161 | |||
162 | #endif |
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163 | |||
569 | jermar | 164 | /** I-/D-TLB Tag Read Register. */ |
165 | union tlb_tag_read_reg { |
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1780 | jermar | 166 | uint64_t value; |
569 | jermar | 167 | struct { |
2054 | jermar | 168 | uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ |
169 | unsigned context : 13; /**< Context identifier. */ |
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569 | jermar | 170 | } __attribute__ ((packed)); |
171 | }; |
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172 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
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613 | jermar | 173 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
569 | jermar | 174 | |
617 | jermar | 175 | |
176 | /** TLB Demap Operation Address. */ |
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177 | union tlb_demap_addr { |
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1780 | jermar | 178 | uint64_t value; |
617 | jermar | 179 | struct { |
1851 | jermar | 180 | uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ |
617 | jermar | 181 | unsigned : 6; /**< Ignored. */ |
182 | unsigned type : 1; /**< The type of demap operation. */ |
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183 | unsigned context : 2; /**< Context register selection. */ |
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184 | unsigned : 4; /**< Zero. */ |
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185 | } __attribute__ ((packed)); |
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186 | }; |
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187 | typedef union tlb_demap_addr tlb_demap_addr_t; |
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188 | |||
873 | jermar | 189 | /** TLB Synchronous Fault Status Register. */ |
190 | union tlb_sfsr_reg { |
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1780 | jermar | 191 | uint64_t value; |
873 | jermar | 192 | struct { |
1851 | jermar | 193 | unsigned long : 40; /**< Implementation dependent. */ |
873 | jermar | 194 | unsigned asi : 8; /**< ASI. */ |
1851 | jermar | 195 | unsigned : 2; |
877 | jermar | 196 | unsigned ft : 7; /**< Fault type. */ |
873 | jermar | 197 | unsigned e : 1; /**< Side-effect bit. */ |
198 | unsigned ct : 2; /**< Context Register selection. */ |
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199 | unsigned pr : 1; /**< Privilege bit. */ |
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200 | unsigned w : 1; /**< Write bit. */ |
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201 | unsigned ow : 1; /**< Overwrite bit. */ |
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877 | jermar | 202 | unsigned fv : 1; /**< Fault Valid bit. */ |
873 | jermar | 203 | } __attribute__ ((packed)); |
204 | }; |
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205 | typedef union tlb_sfsr_reg tlb_sfsr_reg_t; |
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206 | |||
207 | /** Read MMU Primary Context Register. |
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208 | * |
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209 | * @return Current value of Primary Context Register. |
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210 | */ |
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1780 | jermar | 211 | static inline uint64_t mmu_primary_context_read(void) |
873 | jermar | 212 | { |
213 | return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); |
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214 | } |
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215 | |||
216 | /** Write MMU Primary Context Register. |
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217 | * |
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218 | * @param v New value of Primary Context Register. |
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219 | */ |
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1780 | jermar | 220 | static inline void mmu_primary_context_write(uint64_t v) |
873 | jermar | 221 | { |
222 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
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3145 | jermar | 223 | flush_pipeline(); |
873 | jermar | 224 | } |
225 | |||
226 | /** Read MMU Secondary Context Register. |
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227 | * |
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228 | * @return Current value of Secondary Context Register. |
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229 | */ |
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1780 | jermar | 230 | static inline uint64_t mmu_secondary_context_read(void) |
873 | jermar | 231 | { |
232 | return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); |
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233 | } |
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234 | |||
235 | /** Write MMU Primary Context Register. |
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236 | * |
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237 | * @param v New value of Primary Context Register. |
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238 | */ |
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1780 | jermar | 239 | static inline void mmu_secondary_context_write(uint64_t v) |
873 | jermar | 240 | { |
1864 | jermar | 241 | asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v); |
3145 | jermar | 242 | flush_pipeline(); |
873 | jermar | 243 | } |
244 | |||
3440 | rimsky | 245 | #if defined (US) |
246 | |||
569 | jermar | 247 | /** Read IMMU TLB Data Access Register. |
248 | * |
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249 | * @param entry TLB Entry index. |
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250 | * |
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251 | * @return Current value of specified IMMU TLB Data Access Register. |
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252 | */ |
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1780 | jermar | 253 | static inline uint64_t itlb_data_access_read(index_t entry) |
569 | jermar | 254 | { |
3440 | rimsky | 255 | itlb_data_access_addr_t reg; |
569 | jermar | 256 | |
257 | reg.value = 0; |
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258 | reg.tlb_entry = entry; |
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259 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
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260 | } |
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261 | |||
617 | jermar | 262 | /** Write IMMU TLB Data Access Register. |
263 | * |
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264 | * @param entry TLB Entry index. |
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265 | * @param value Value to be written. |
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266 | */ |
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1780 | jermar | 267 | static inline void itlb_data_access_write(index_t entry, uint64_t value) |
617 | jermar | 268 | { |
3440 | rimsky | 269 | itlb_data_access_addr_t reg; |
617 | jermar | 270 | |
271 | reg.value = 0; |
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272 | reg.tlb_entry = entry; |
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273 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
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3145 | jermar | 274 | flush_pipeline(); |
617 | jermar | 275 | } |
276 | |||
569 | jermar | 277 | /** Read DMMU TLB Data Access Register. |
278 | * |
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279 | * @param entry TLB Entry index. |
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280 | * |
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281 | * @return Current value of specified DMMU TLB Data Access Register. |
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282 | */ |
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1780 | jermar | 283 | static inline uint64_t dtlb_data_access_read(index_t entry) |
569 | jermar | 284 | { |
3440 | rimsky | 285 | dtlb_data_access_addr_t reg; |
569 | jermar | 286 | |
287 | reg.value = 0; |
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288 | reg.tlb_entry = entry; |
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289 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
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290 | } |
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291 | |||
617 | jermar | 292 | /** Write DMMU TLB Data Access Register. |
293 | * |
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294 | * @param entry TLB Entry index. |
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295 | * @param value Value to be written. |
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296 | */ |
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1780 | jermar | 297 | static inline void dtlb_data_access_write(index_t entry, uint64_t value) |
617 | jermar | 298 | { |
3440 | rimsky | 299 | dtlb_data_access_addr_t reg; |
617 | jermar | 300 | |
301 | reg.value = 0; |
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302 | reg.tlb_entry = entry; |
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303 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
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1822 | jermar | 304 | membar(); |
617 | jermar | 305 | } |
306 | |||
569 | jermar | 307 | /** Read IMMU TLB Tag Read Register. |
308 | * |
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309 | * @param entry TLB Entry index. |
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310 | * |
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311 | * @return Current value of specified IMMU TLB Tag Read Register. |
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312 | */ |
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1780 | jermar | 313 | static inline uint64_t itlb_tag_read_read(index_t entry) |
569 | jermar | 314 | { |
3440 | rimsky | 315 | itlb_tag_read_addr_t tag; |
569 | jermar | 316 | |
317 | tag.value = 0; |
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318 | tag.tlb_entry = entry; |
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319 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
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320 | } |
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321 | |||
322 | /** Read DMMU TLB Tag Read Register. |
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323 | * |
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324 | * @param entry TLB Entry index. |
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325 | * |
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326 | * @return Current value of specified DMMU TLB Tag Read Register. |
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327 | */ |
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1780 | jermar | 328 | static inline uint64_t dtlb_tag_read_read(index_t entry) |
569 | jermar | 329 | { |
3440 | rimsky | 330 | dtlb_tag_read_addr_t tag; |
569 | jermar | 331 | |
332 | tag.value = 0; |
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333 | tag.tlb_entry = entry; |
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334 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
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335 | } |
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336 | |||
3440 | rimsky | 337 | #elif defined (US3) |
338 | |||
339 | |||
340 | /** Read IMMU TLB Data Access Register. |
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341 | * |
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342 | * @param tlb TLB number (one of TLB_IT16 or TLB_IT128) |
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343 | * @param entry TLB Entry index. |
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344 | * |
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345 | * @return Current value of specified IMMU TLB Data Access Register. |
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346 | */ |
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347 | static inline uint64_t itlb_data_access_read(int tlb, index_t entry) |
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348 | { |
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349 | itlb_data_access_addr_t reg; |
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350 | |||
351 | reg.value = 0; |
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352 | reg.tlb_number = tlb; |
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353 | reg.local_tlb_entry = entry; |
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354 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
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355 | } |
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356 | |||
357 | /** Write IMMU TLB Data Access Register. |
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358 | * @param tlb TLB number (one of TLB_IT16 or TLB_IT128) |
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359 | * @param entry TLB Entry index. |
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360 | * @param value Value to be written. |
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361 | */ |
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362 | static inline void itlb_data_access_write(int tlb, index_t entry, uint64_t value) |
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363 | { |
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364 | itlb_data_access_addr_t reg; |
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365 | |||
366 | reg.value = 0; |
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367 | reg.tlb_number = tlb; |
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368 | reg.local_tlb_entry = entry; |
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369 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
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370 | flush_pipeline(); |
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371 | } |
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372 | |||
373 | /** Read DMMU TLB Data Access Register. |
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374 | * |
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375 | * @param tlb TLB number (one of TLB_DT16, TLB_DT512_1, TLB_DT512_2) |
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376 | * @param entry TLB Entry index. |
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377 | * |
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378 | * @return Current value of specified DMMU TLB Data Access Register. |
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379 | */ |
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380 | static inline uint64_t dtlb_data_access_read(int tlb, index_t entry) |
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381 | { |
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382 | dtlb_data_access_addr_t reg; |
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383 | |||
384 | reg.value = 0; |
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385 | reg.tlb_number = tlb; |
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386 | reg.local_tlb_entry = entry; |
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387 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
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388 | } |
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389 | |||
390 | /** Write DMMU TLB Data Access Register. |
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391 | * |
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392 | * @param tlb TLB number (one of TLB_DT16, TLB_DT512_1, TLB_DT512_2) |
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393 | * @param entry TLB Entry index. |
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394 | * @param value Value to be written. |
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395 | */ |
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396 | static inline void dtlb_data_access_write(int tlb, index_t entry, uint64_t value) |
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397 | { |
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398 | dtlb_data_access_addr_t reg; |
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399 | |||
400 | reg.value = 0; |
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401 | reg.tlb_number = tlb; |
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402 | reg.local_tlb_entry = entry; |
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403 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
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404 | membar(); |
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405 | } |
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406 | |||
407 | /** Read IMMU TLB Tag Read Register. |
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408 | * |
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409 | * @param tlb TLB number (one of TLB_IT16 or TLB_IT128) |
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410 | * @param entry TLB Entry index. |
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411 | * |
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412 | * @return Current value of specified IMMU TLB Tag Read Register. |
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413 | */ |
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414 | static inline uint64_t itlb_tag_read_read(int tlb, index_t entry) |
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415 | { |
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416 | itlb_tag_read_addr_t tag; |
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417 | |||
418 | tag.value = 0; |
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419 | tag.tlb_number = tlb; |
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420 | tag.local_tlb_entry = entry; |
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421 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
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422 | } |
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423 | |||
424 | /** Read DMMU TLB Tag Read Register. |
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425 | * |
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426 | * @param tlb TLB number (one of TLB_DT16, TLB_DT512_1, TLB_DT512_2) |
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427 | * @param entry TLB Entry index. |
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428 | * |
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429 | * @return Current value of specified DMMU TLB Tag Read Register. |
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430 | */ |
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431 | static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry) |
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432 | { |
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433 | dtlb_tag_read_addr_t tag; |
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434 | |||
435 | tag.value = 0; |
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436 | tag.tlb_number = tlb; |
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437 | tag.local_tlb_entry = entry; |
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438 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
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439 | } |
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440 | |||
441 | #endif |
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442 | |||
443 | |||
613 | jermar | 444 | /** Write IMMU TLB Tag Access Register. |
445 | * |
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446 | * @param v Value to be written. |
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447 | */ |
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1780 | jermar | 448 | static inline void itlb_tag_access_write(uint64_t v) |
613 | jermar | 449 | { |
450 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
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3145 | jermar | 451 | flush_pipeline(); |
613 | jermar | 452 | } |
453 | |||
877 | jermar | 454 | /** Read IMMU TLB Tag Access Register. |
455 | * |
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456 | * @return Current value of IMMU TLB Tag Access Register. |
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457 | */ |
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1780 | jermar | 458 | static inline uint64_t itlb_tag_access_read(void) |
877 | jermar | 459 | { |
460 | return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); |
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461 | } |
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462 | |||
613 | jermar | 463 | /** Write DMMU TLB Tag Access Register. |
464 | * |
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465 | * @param v Value to be written. |
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466 | */ |
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1780 | jermar | 467 | static inline void dtlb_tag_access_write(uint64_t v) |
613 | jermar | 468 | { |
469 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
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1822 | jermar | 470 | membar(); |
613 | jermar | 471 | } |
472 | |||
877 | jermar | 473 | /** Read DMMU TLB Tag Access Register. |
474 | * |
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475 | * @return Current value of DMMU TLB Tag Access Register. |
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476 | */ |
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1780 | jermar | 477 | static inline uint64_t dtlb_tag_access_read(void) |
877 | jermar | 478 | { |
479 | return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); |
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480 | } |
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481 | |||
482 | |||
613 | jermar | 483 | /** Write IMMU TLB Data in Register. |
484 | * |
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485 | * @param v Value to be written. |
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486 | */ |
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1780 | jermar | 487 | static inline void itlb_data_in_write(uint64_t v) |
613 | jermar | 488 | { |
489 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
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3145 | jermar | 490 | flush_pipeline(); |
613 | jermar | 491 | } |
492 | |||
493 | /** Write DMMU TLB Data in Register. |
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494 | * |
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495 | * @param v Value to be written. |
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496 | */ |
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1780 | jermar | 497 | static inline void dtlb_data_in_write(uint64_t v) |
613 | jermar | 498 | { |
499 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
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1822 | jermar | 500 | membar(); |
613 | jermar | 501 | } |
502 | |||
873 | jermar | 503 | /** Read ITLB Synchronous Fault Status Register. |
504 | * |
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505 | * @return Current content of I-SFSR register. |
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506 | */ |
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1780 | jermar | 507 | static inline uint64_t itlb_sfsr_read(void) |
873 | jermar | 508 | { |
509 | return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); |
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510 | } |
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511 | |||
512 | /** Write ITLB Synchronous Fault Status Register. |
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513 | * |
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514 | * @param v New value of I-SFSR register. |
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515 | */ |
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1780 | jermar | 516 | static inline void itlb_sfsr_write(uint64_t v) |
873 | jermar | 517 | { |
518 | asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); |
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3145 | jermar | 519 | flush_pipeline(); |
873 | jermar | 520 | } |
521 | |||
522 | /** Read DTLB Synchronous Fault Status Register. |
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523 | * |
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524 | * @return Current content of D-SFSR register. |
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525 | */ |
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1780 | jermar | 526 | static inline uint64_t dtlb_sfsr_read(void) |
873 | jermar | 527 | { |
528 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); |
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529 | } |
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530 | |||
531 | /** Write DTLB Synchronous Fault Status Register. |
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532 | * |
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533 | * @param v New value of D-SFSR register. |
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534 | */ |
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1780 | jermar | 535 | static inline void dtlb_sfsr_write(uint64_t v) |
873 | jermar | 536 | { |
537 | asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); |
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1822 | jermar | 538 | membar(); |
873 | jermar | 539 | } |
540 | |||
541 | /** Read DTLB Synchronous Fault Address Register. |
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542 | * |
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543 | * @return Current content of D-SFAR register. |
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544 | */ |
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1780 | jermar | 545 | static inline uint64_t dtlb_sfar_read(void) |
873 | jermar | 546 | { |
547 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
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548 | } |
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549 | |||
617 | jermar | 550 | /** Perform IMMU TLB Demap Operation. |
551 | * |
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552 | * @param type Selects between context and page demap. |
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2054 | jermar | 553 | * @param context_encoding Specifies which Context register has Context ID for |
554 | * demap. |
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617 | jermar | 555 | * @param page Address which is on the page to be demapped. |
556 | */ |
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1780 | jermar | 557 | static inline void itlb_demap(int type, int context_encoding, uintptr_t page) |
617 | jermar | 558 | { |
559 | tlb_demap_addr_t da; |
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560 | page_address_t pg; |
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561 | |||
562 | da.value = 0; |
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563 | pg.address = page; |
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564 | |||
565 | da.type = type; |
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566 | da.context = context_encoding; |
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567 | da.vpn = pg.vpn; |
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568 | |||
2054 | jermar | 569 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the |
570 | * address within the |
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571 | * ASI */ |
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3145 | jermar | 572 | flush_pipeline(); |
617 | jermar | 573 | } |
574 | |||
575 | /** Perform DMMU TLB Demap Operation. |
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576 | * |
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577 | * @param type Selects between context and page demap. |
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2054 | jermar | 578 | * @param context_encoding Specifies which Context register has Context ID for |
579 | * demap. |
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617 | jermar | 580 | * @param page Address which is on the page to be demapped. |
581 | */ |
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1780 | jermar | 582 | static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) |
617 | jermar | 583 | { |
584 | tlb_demap_addr_t da; |
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585 | page_address_t pg; |
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586 | |||
587 | da.value = 0; |
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588 | pg.address = page; |
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589 | |||
590 | da.type = type; |
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591 | da.context = context_encoding; |
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592 | da.vpn = pg.vpn; |
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593 | |||
2054 | jermar | 594 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the |
595 | * address within the |
||
596 | * ASI */ |
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1822 | jermar | 597 | membar(); |
617 | jermar | 598 | } |
599 | |||
2231 | jermar | 600 | extern void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate); |
601 | extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate); |
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602 | extern void fast_data_access_protection(tlb_tag_access_reg_t tag , istate_t *istate); |
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863 | jermar | 603 | |
1780 | jermar | 604 | extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable); |
897 | jermar | 605 | |
1946 | jermar | 606 | extern void dump_sfsr_and_sfar(void); |
607 | |||
1823 | jermar | 608 | #endif /* !def __ASM__ */ |
609 | |||
418 | jermar | 610 | #endif |
1702 | cejka | 611 | |
1822 | jermar | 612 | /** @} |
3440 | rimsky | 613 | */ |