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3771 rimsky 1 
/*
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 * Copyright (c) 2005 Jakub Jermar
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 * Copyright (c) 2008 Pavel Rimsky
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup sparc64mm  
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 * @{
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 */
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/** @file
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 */
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#ifndef KERN_sparc64_sun4v_TLB_H_
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#define KERN_sparc64_sun4v_TLB_H_
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3835 rimsky 39 
#define MMU_FSA_ALIGNMENT   64
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#define MMU_FSA_SIZE        128
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3771 rimsky 42 
#ifndef __ASM__
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#include <arch/mm/tte.h>
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#include <arch/mm/mmu.h>
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#include <arch/mm/page.h>
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#include <arch/asm.h>
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#include <arch/barrier.h>
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#include <arch/types.h>
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#include <arch/register.h>
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#include <arch/cpu.h>
3862 rimsky 52 
#include <arch/sun4v/hypercall.h>
3771 rimsky 53 
 
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/**
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 * Structure filled by hypervisor (or directly CPU, if implemented so) when
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 * a MMU fault occurs. The structure describes the exact condition which
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 * has caused the fault.
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 */
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typedef struct mmu_fault_status_area {
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    uint64_t ift;       /**< Instruction fault type (IFT) */
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    uint64_t ifa;       /**< Instruction fault address (IFA) */
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    uint64_t ifc;       /**< Instruction fault context (IFC) */
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    uint8_t reserved1[0x28];
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    uint64_t dft;       /**< Data fault type (DFT) */
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    uint64_t dfa;       /**< Data fault address (DFA) */
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    uint64_t dfc;       /**< Data fault context (DFC) */
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    uint8_t reserved2[0x28];
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} __attribute__ ((packed)) mmu_fault_status_area_t;
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3862 rimsky 71 
#define DTLB_MAX_LOCKED_ENTRIES     8
3771 rimsky 72 
 
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/** Bit width of the TLB-locked portion of kernel address space. */
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#define KERNEL_PAGE_WIDTH       22  /* 4M */
3771 rimsky 75 
 
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/*
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 * Reading and writing context registers.
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 *
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 * Note that UltraSPARC Architecture-compatible processors do not require
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 * a MEMBAR #Sync, FLUSH, DONE, or RETRY instruction after a store to an
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 * MMU register for proper operation.
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 *
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 */
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/** Read MMU Primary Context Register.
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 *
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 * @return  Current value of Primary Context Register.
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 */
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static inline uint64_t mmu_primary_context_read(void)
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{
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    return asi_u64_read(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG);
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}
3862 rimsky 93 
 
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/** Write MMU Primary Context Register.
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 *
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 * @param v New value of Primary Context Register.
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 */
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static inline void mmu_primary_context_write(uint64_t v)
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{
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    asi_u64_write(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG, v);
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}
3862 rimsky 102 
 
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/** Read MMU Secondary Context Register.
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 *
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 * @return  Current value of Secondary Context Register.
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 */
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static inline uint64_t mmu_secondary_context_read(void)
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{
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    return asi_u64_read(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG);
3771 rimsky 110 
}
3862 rimsky 111 
 
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/** Write MMU Secondary Context Register.
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 *
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 * @param v New value of Secondary Context Register.
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 */
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static inline void mmu_secondary_context_write(uint64_t v)
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{
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    asi_u64_write(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG, v);
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}
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/** Perform IMMU TLB Demap Operation.
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 *
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 * @param type      Selects between context and page demap (and entire MMU
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 *          demap on US3).
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 * @param context_encoding Specifies which Context register has Context ID for
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 *          demap.
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 * @param page      Address which is on the page to be demapped.
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 */
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static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
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{
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}
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/** Perform DMMU TLB Demap Operation.
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 *
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 * @param type      One of TLB_DEMAP_PAGE and TLB_DEMAP_CONTEXT. Selects
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 *          between context and page demap.
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 * @param context_encoding Specifies which Context register has Context ID for
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 *          demap.
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 * @param page      Address which is on the page to be demapped.
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 */
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static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
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{
3862 rimsky 143 
    #if 0
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         - this implementation is not correct!!!
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    if (type == TLB_DEMAP_PAGE) {
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        __hypercall_fast5(
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            MMU_DEMAP_PAGE, 0, 0,
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            page, context_encoding, MMU_FLAG_DTLB);
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    } else if (type == TLB_DEMAP_CONTEXT) {
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        __hypercall_fast4(
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            MMU_DEMAP_CTX, 0, 0,
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            context_encoding, MMU_FLAG_DTLB);
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    }
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    #endif
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}
3771 rimsky 156 
 
3862 rimsky 157 
/**
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 * Demaps all mappings in a context.
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 *
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 * @param context   number of the context
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 * @param mmu_flag  MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both
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 */
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static inline void mmu_demap_ctx(int context, int mmu_flag) {
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    __hypercall_fast4(MMU_DEMAP_CTX, 0, 0, context, mmu_flag);
3771 rimsky 165 
}
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3862 rimsky 167 
static inline void mmu_demap_page(uintptr_t vaddr, int context, int mmu_flag) {
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    __hypercall_fast5(MMU_DEMAP_PAGE, 0, 0, vaddr, context, mmu_flag);
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}
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static inline void mmu_map_perm_addr(uintptr_t vaddr, uintptr_t ra,
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        bool cacheable, bool privileged, bool executable,
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        bool writable, unsigned size, unsigned mmu_flags) {
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    tte_data_t data;
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    data.value = 0;
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    data.v = true;
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    data.ra = ra;
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    data.cp = data.cv = cacheable;
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    data.p = privileged;
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    data.x = executable;
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    data.w = writable;
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    data.size = size;
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    __hypercall_fast4(MMU_MAP_PERM_ADDR, vaddr, 0, data.value, mmu_flags);
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}
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3771 rimsky 189 
extern void fast_instruction_access_mmu_miss(unative_t, istate_t *);
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extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);
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extern void describe_mmu_fault(void);
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#endif /* !def __ASM__ */
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#endif
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/** @}
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 */