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418 jermar 1
/*
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 * Copyright (C) 2005 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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1702 cejka 29
 /** @addtogroup sparc64   
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 * @{
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 */
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/** @file
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 */
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418 jermar 35
#ifndef __sparc64_ASM_H__
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#define __sparc64_ASM_H__
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650 jermar 38
#include <typedefs.h>
418 jermar 39
#include <arch/types.h>
650 jermar 40
#include <arch/register.h>
418 jermar 41
#include <config.h>
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650 jermar 43
/** Read Processor State register.
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 *
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 * @return Value of PSTATE register.
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 */
1780 jermar 47
static inline uint64_t pstate_read(void)
650 jermar 48
{
1780 jermar 49
    uint64_t v;
650 jermar 50
 
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    __asm__ volatile ("rdpr %%pstate, %0\n" : "=r" (v));
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    return v;
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}
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/** Write Processor State register.
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 *
1708 jermar 58
 * @param v New value of PSTATE register.
650 jermar 59
 */
1780 jermar 60
static inline void pstate_write(uint64_t v)
650 jermar 61
{
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    __asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
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}
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658 jermar 65
/** Read TICK_compare Register.
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 *
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 * @return Value of TICK_comapre register.
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 */
1780 jermar 69
static inline uint64_t tick_compare_read(void)
658 jermar 70
{
1780 jermar 71
    uint64_t v;
658 jermar 72
 
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    __asm__ volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
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75
    return v;
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}
650 jermar 77
 
658 jermar 78
/** Write TICK_compare Register.
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 *
1708 jermar 80
 * @param v New value of TICK_comapre register.
658 jermar 81
 */
1780 jermar 82
static inline void tick_compare_write(uint64_t v)
658 jermar 83
{
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    __asm__ volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
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}
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/** Read TICK Register.
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 *
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 * @return Value of TICK register.
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 */
1780 jermar 91
static inline uint64_t tick_read(void)
658 jermar 92
{
1780 jermar 93
    uint64_t v;
658 jermar 94
 
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    __asm__ volatile ("rdpr %%tick, %0\n" : "=r" (v));
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97
    return v;
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}
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/** Write TICK Register.
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 *
1708 jermar 102
 * @param v New value of TICK register.
658 jermar 103
 */
1780 jermar 104
static inline void tick_write(uint64_t v)
658 jermar 105
{
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    __asm__ volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
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}
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664 jermar 109
/** Read SOFTINT Register.
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 *
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 * @return Value of SOFTINT register.
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 */
1780 jermar 113
static inline uint64_t softint_read(void)
664 jermar 114
{
1780 jermar 115
    uint64_t v;
658 jermar 116
 
664 jermar 117
    __asm__ volatile ("rd %%softint, %0\n" : "=r" (v));
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119
    return v;
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}
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122
/** Write SOFTINT Register.
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 *
1708 jermar 124
 * @param v New value of SOFTINT register.
664 jermar 125
 */
1780 jermar 126
static inline void softint_write(uint64_t v)
664 jermar 127
{
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    __asm__ volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
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}
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665 jermar 131
/** Write CLEAR_SOFTINT Register.
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 *
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 * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.
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 *
1708 jermar 135
 * @param v New value of CLEAR_SOFTINT register.
665 jermar 136
 */
1780 jermar 137
static inline void clear_softint_write(uint64_t v)
665 jermar 138
{
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    __asm__ volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
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}
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418 jermar 142
/** Enable interrupts.
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 *
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 * Enable interrupts and return previous
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 * value of IPL.
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 *
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 * @return Old interrupt priority level.
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 */
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static inline ipl_t interrupts_enable(void) {
650 jermar 150
    pstate_reg_t pstate;
1780 jermar 151
    uint64_t value;
650 jermar 152
 
153
    value = pstate_read();
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    pstate.value = value;
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    pstate.ie = true;
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    pstate_write(pstate.value);
157
 
158
    return (ipl_t) value;
418 jermar 159
}
160
 
161
/** Disable interrupts.
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 *
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 * Disable interrupts and return previous
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 * value of IPL.
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 *
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 * @return Old interrupt priority level.
167
 */
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static inline ipl_t interrupts_disable(void) {
650 jermar 169
    pstate_reg_t pstate;
1780 jermar 170
    uint64_t value;
650 jermar 171
 
172
    value = pstate_read();
173
    pstate.value = value;
174
    pstate.ie = false;
175
    pstate_write(pstate.value);
176
 
177
    return (ipl_t) value;
418 jermar 178
}
179
 
180
/** Restore interrupt priority level.
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 *
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 * Restore IPL.
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 *
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 * @param ipl Saved interrupt priority level.
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 */
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static inline void interrupts_restore(ipl_t ipl) {
650 jermar 187
    pstate_reg_t pstate;
188
 
189
    pstate.value = pstate_read();
190
    pstate.ie = ((pstate_reg_t) ipl).ie;
191
    pstate_write(pstate.value);
418 jermar 192
}
193
 
194
/** Return interrupt priority level.
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 *
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 * Return IPL.
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 *
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 * @return Current interrupt priority level.
199
 */
200
static inline ipl_t interrupts_read(void) {
650 jermar 201
    return (ipl_t) pstate_read();
418 jermar 202
}
203
 
204
/** Return base address of current stack.
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 *
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 * Return the base address of the current stack.
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 * The stack is assumed to be STACK_SIZE bytes long.
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 * The stack must start on page boundary.
209
 */
1780 jermar 210
static inline uintptr_t get_stack_base(void)
418 jermar 211
{
1780 jermar 212
    uintptr_t v;
426 jermar 213
 
650 jermar 214
    __asm__ volatile ("and %%sp, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
426 jermar 215
 
216
    return v;
418 jermar 217
}
218
 
640 jermar 219
/** Read Version Register.
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 *
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 * @return Value of VER register.
222
 */
1780 jermar 223
static inline uint64_t ver_read(void)
640 jermar 224
{
1780 jermar 225
    uint64_t v;
640 jermar 226
 
227
    __asm__ volatile ("rdpr %%ver, %0\n" : "=r" (v));
228
 
229
    return v;
230
}
231
 
529 jermar 232
/** Read Trap Base Address register.
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 *
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 * @return Current value in TBA.
235
 */
1780 jermar 236
static inline uint64_t tba_read(void)
529 jermar 237
{
1780 jermar 238
    uint64_t v;
529 jermar 239
 
240
    __asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v));
241
 
242
    return v;
243
}
244
 
873 jermar 245
/** Read Trap Program Counter register.
246
 *
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 * @return Current value in TPC.
248
 */
1780 jermar 249
static inline uint64_t tpc_read(void)
873 jermar 250
{
1780 jermar 251
    uint64_t v;
873 jermar 252
 
253
    __asm__ volatile ("rdpr %%tpc, %0\n" : "=r" (v));
254
 
255
    return v;
256
}
257
 
883 jermar 258
/** Read Trap Level register.
259
 *
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 * @return Current value in TL.
261
 */
1780 jermar 262
static inline uint64_t tl_read(void)
883 jermar 263
{
1780 jermar 264
    uint64_t v;
883 jermar 265
 
266
    __asm__ volatile ("rdpr %%tl, %0\n" : "=r" (v));
267
 
268
    return v;
269
}
873 jermar 270
 
529 jermar 271
/** Write Trap Base Address register.
272
 *
1708 jermar 273
 * @param v New value of TBA.
529 jermar 274
 */
1780 jermar 275
static inline void tba_write(uint64_t v)
529 jermar 276
{
277
    __asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
278
}
279
 
1780 jermar 280
/** Load uint64_t from alternate space.
569 jermar 281
 *
282
 * @param asi ASI determining the alternate space.
283
 * @param va Virtual address within the ASI.
284
 *
285
 * @return Value read from the virtual address in the specified address space.
286
 */
1780 jermar 287
static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
569 jermar 288
{
1780 jermar 289
    uint64_t v;
569 jermar 290
 
291
    __asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" (asi));
292
 
293
    return v;
294
}
529 jermar 295
 
1780 jermar 296
/** Store uint64_t to alternate space.
569 jermar 297
 *
298
 * @param asi ASI determining the alternate space.
299
 * @param va Virtual address within the ASI.
300
 * @param v Value to be written.
301
 */
1780 jermar 302
static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
569 jermar 303
{
613 jermar 304
    __asm__ volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" (asi) : "memory");
569 jermar 305
}
306
 
658 jermar 307
 
308
 
418 jermar 309
void cpu_halt(void);
310
void cpu_sleep(void);
1780 jermar 311
void asm_delay_loop(uint32_t t);
418 jermar 312
 
313
#endif
1702 cejka 314
 
315
 /** @}
316
 */
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