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1 jermar 1
/*
2071 jermar 2
 * Copyright (c) 2001-2004 Jakub Jermar
1 jermar 3
 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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1888 jermar 29
/** @addtogroup ia32   
1702 cejka 30
 * @{
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 */
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/** @file
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 */
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1 jermar 35
#include <arch/pm.h>
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#include <config.h>
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#include <arch/types.h>
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#include <arch/interrupt.h>
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#include <arch/asm.h>
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#include <arch/context.h>
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#include <panic.h>
167 jermar 42
#include <arch/mm/page.h>
814 palkovsky 43
#include <mm/slab.h>
195 vana 44
#include <memstr.h>
244 decky 45
#include <arch/boot/boot.h>
576 palkovsky 46
#include <interrupt.h>
1 jermar 47
 
48
/*
11 jermar 49
 * Early ia32 configuration functions and data structures.
1 jermar 50
 */
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52
/*
53
 * We have no use for segmentation so we set up flat mode. In this
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 * mode, we use, for each privilege level, two segments spanning the
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 * whole memory. One is for code and one is for data.
1112 palkovsky 56
 *
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 * One is for GS register which holds pointer to the TLS thread
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 * structure in it's base.
1 jermar 59
 */
1187 jermar 60
descriptor_t gdt[GDT_ITEMS] = {
125 jermar 61
    /* NULL descriptor */
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    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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    /* KTEXT descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
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    /* KDATA descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
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    /* UTEXT descriptor */
68
    { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
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    /* UDATA descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
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    /* TSS descriptor - set up will be completed later */
1112 palkovsky 72
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1189 jermar 73
    /* TLS descriptor */
1287 vana 74
    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
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    /* VESA Init descriptor */
1292 vana 76
#ifdef CONFIG_FB
1289 vana 77
    { 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
1292 vana 78
#endif  
1 jermar 79
};
80
 
1187 jermar 81
static idescriptor_t idt[IDT_ITEMS];
1 jermar 82
 
1187 jermar 83
static tss_t tss;
1 jermar 84
 
1187 jermar 85
tss_t *tss_p = NULL;
1 jermar 86
 
22 jermar 87
/* gdtr is changed by kmp before next CPU is initialized */
1780 jermar 88
ptr_16_32_t bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((uintptr_t) gdt) };
89
ptr_16_32_t gdtr = { .limit = sizeof(gdt), .base = (uintptr_t) gdt };
1 jermar 90
 
1780 jermar 91
void gdt_setbase(descriptor_t *d, uintptr_t base)
1 jermar 92
{
125 jermar 93
    d->base_0_15 = base & 0xffff;
94
    d->base_16_23 = ((base) >> 16) & 0xff;
95
    d->base_24_31 = ((base) >> 24) & 0xff;
1 jermar 96
}
97
 
1780 jermar 98
void gdt_setlimit(descriptor_t *d, uint32_t limit)
1 jermar 99
{
125 jermar 100
    d->limit_0_15 = limit & 0xffff;
101
    d->limit_16_19 = (limit >> 16) & 0xf;
1 jermar 102
}
103
 
1780 jermar 104
void idt_setoffset(idescriptor_t *d, uintptr_t offset)
1 jermar 105
{
112 jermar 106
    /*
107
     * Offset is a linear address.
108
     */
109
    d->offset_0_15 = offset & 0xffff;
110
    d->offset_16_31 = offset >> 16;
1 jermar 111
}
112
 
1187 jermar 113
void tss_initialize(tss_t *t)
1 jermar 114
{
1780 jermar 115
    memsetb((uintptr_t) t, sizeof(struct tss), 0);
1 jermar 116
}
117
 
118
/*
119
 * This function takes care of proper setup of IDT and IDTR.
120
 */
121
void idt_init(void)
122
{
1187 jermar 123
    idescriptor_t *d;
2307 hudecek 124
    unsigned int i;
125 jermar 125
 
1 jermar 126
    for (i = 0; i < IDT_ITEMS; i++) {
127
        d = &idt[i];
128
 
129
        d->unused = 0;
130
        d->selector = selector(KTEXT_DES);
131
 
132
        d->access = AR_PRESENT | AR_INTERRUPT;  /* masking interrupt */
133
 
134
        if (i == VECTOR_SYSCALL) {
135
            /*
136
             * The syscall interrupt gate must be calleable from userland.
137
             */
138
            d->access |= DPL_USER;
139
        }
140
 
1956 decky 141
        idt_setoffset(d, ((uintptr_t) interrupt_handlers) + i * interrupt_handler_size);
1 jermar 142
    }
143
}
144
 
145
 
144 vana 146
/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
141 vana 147
static void clean_IOPL_NT_flags(void)
148
{
2082 decky 149
    asm volatile (
1187 jermar 150
        "pushfl\n"
151
        "pop %%eax\n"
152
        "and $0xffff8fff, %%eax\n"
153
        "push %%eax\n"
154
        "popfl\n"
155
        : : : "eax"
141 vana 156
    );
157
}
158
 
144 vana 159
/* Clean AM(18) flag in CR0 register */
143 vana 160
static void clean_AM_flag(void)
161
{
2082 decky 162
    asm volatile (
1187 jermar 163
        "mov %%cr0, %%eax\n"
164
        "and $0xfffbffff, %%eax\n"
165
        "mov %%eax, %%cr0\n"
166
        : : : "eax"
143 vana 167
    );
168
}
141 vana 169
 
1 jermar 170
void pm_init(void)
171
{
1187 jermar 172
    descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
173
    ptr_16_32_t idtr;
1 jermar 174
 
175
    /*
232 jermar 176
     * Update addresses in GDT and IDT to their virtual counterparts.
177
     */
271 decky 178
    idtr.limit = sizeof(idt);
1780 jermar 179
    idtr.base = (uintptr_t) idt;
1186 jermar 180
    gdtr_load(&gdtr);
181
    idtr_load(&idtr);
232 jermar 182
 
183
    /*
1 jermar 184
     * Each CPU has its private GDT and TSS.
185
     * All CPUs share one IDT.
186
     */
187
 
188
    if (config.cpu_active == 1) {
189
        idt_init();
190
        /*
191
         * NOTE: bootstrap CPU has statically allocated TSS, because
192
         * the heap hasn't been initialized so far.
193
         */
194
        tss_p = &tss;
195
    }
196
    else {
1187 jermar 197
        tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
1 jermar 198
        if (!tss_p)
68 decky 199
            panic("could not allocate TSS\n");
1 jermar 200
    }
201
 
202
    tss_initialize(tss_p);
203
 
204
    gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
205
    gdt_p[TSS_DES].special = 1;
1251 jermar 206
    gdt_p[TSS_DES].granularity = 0;
1 jermar 207
 
1780 jermar 208
    gdt_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
1251 jermar 209
    gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
1 jermar 210
 
211
    /*
212
     * As of this moment, the current CPU has its own GDT pointing
213
     * to its own TSS. We just need to load the TR register.
214
     */
1186 jermar 215
    tr_load(selector(TSS_DES));
141 vana 216
 
1251 jermar 217
    clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels and clear NT flag. */
144 vana 218
    clean_AM_flag();          /* Disable alignment check */
1 jermar 219
}
1112 palkovsky 220
 
1780 jermar 221
void set_tls_desc(uintptr_t tls)
1112 palkovsky 222
{
1187 jermar 223
    ptr_16_32_t cpugdtr;
1188 jermar 224
    descriptor_t *gdt_p;
1112 palkovsky 225
 
1186 jermar 226
    gdtr_store(&cpugdtr);
1188 jermar 227
    gdt_p = (descriptor_t *) cpugdtr.base;
1112 palkovsky 228
    gdt_setbase(&gdt_p[TLS_DES], tls);
229
    /* Reload gdt register to update GS in CPU */
1186 jermar 230
    gdtr_load(&cpugdtr);
1112 palkovsky 231
}
1702 cejka 232
 
2307 hudecek 233
/* Reboot the machine by initiating
234
 * a triple fault
235
 */
236
void arch_reboot(void)
237
{
238
    preemption_disable();
239
    ipl_t ipl = interrupts_disable();
240
 
241
    memsetb((uintptr_t) idt, sizeof(idt), 0);
242
 
243
    ptr_16_32_t idtr;
244
    idtr.limit = sizeof(idt);
245
    idtr.base = (uintptr_t) idt;
246
    idtr_load(&idtr);
247
 
248
    interrupts_restore(ipl);
249
    asm volatile (
250
        "int $0x03\n"
251
        "cli\n"
252
        "hlt\n"
253
    );
254
}
255
 
1888 jermar 256
/** @}
1702 cejka 257
 */