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173 jermar 1
/*
2071 jermar 2
 * Copyright (c) 2005 Jakub Jermar
173 jermar 3
 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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1888 jermar 29
/** @addtogroup amd64  
1702 cejka 30
 * @{
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 */
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/** @file
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 */
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1888 jermar 35
#ifndef KERN_amd64_ASM_H_
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#define KERN_amd64_ASM_H_
173 jermar 37
 
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#include <config.h>
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1780 jermar 40
extern void asm_delay_loop(uint32_t t);
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extern void asm_fake_loop(uint32_t t);
200 palkovsky 42
 
253 jermar 43
/** Return base address of current stack.
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 *
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 * Return the base address of the current stack.
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 * The stack is assumed to be STACK_SIZE bytes long.
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 * The stack must start on page boundary.
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 */
1780 jermar 49
static inline uintptr_t get_stack_base(void)
173 jermar 50
{
1780 jermar 51
    uintptr_t v;
226 palkovsky 52
 
2082 decky 53
    asm volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((uint64_t)STACK_SIZE-1)));
226 palkovsky 54
 
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    return v;
173 jermar 56
}
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2307 hudecek 58
static inline void cpu_sleep(void)
59
{
60
    asm volatile ("hlt\n");
61
};
197 palkovsky 62
 
2307 hudecek 63
static inline void cpu_halt(void)
64
{
65
    asm volatile ("hlt\n");
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};
200 palkovsky 67
 
2307 hudecek 68
 
625 palkovsky 69
/** Byte from port
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 *
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 * Get byte from port
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 *
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 * @param port Port to read from
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 * @return Value read
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 */
1780 jermar 76
static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
200 palkovsky 77
 
625 palkovsky 78
/** Byte to port
79
 *
80
 * Output byte to port
81
 *
82
 * @param port Port to write to
83
 * @param val Value to write
84
 */
1780 jermar 85
static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
200 palkovsky 86
 
806 palkovsky 87
/** Swap Hidden part of GS register with visible one */
88
static inline void swapgs(void) { __asm__ volatile("swapgs"); }
89
 
413 jermar 90
/** Enable interrupts.
200 palkovsky 91
 *
92
 * Enable interrupts and return previous
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 * value of EFLAGS.
413 jermar 94
 *
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 * @return Old interrupt priority level.
200 palkovsky 96
 */
413 jermar 97
static inline ipl_t interrupts_enable(void) {
98
    ipl_t v;
200 palkovsky 99
    __asm__ volatile (
100
        "pushfq\n"
101
        "popq %0\n"
102
        "sti\n"
103
        : "=r" (v)
104
    );
105
    return v;
106
}
107
 
413 jermar 108
/** Disable interrupts.
200 palkovsky 109
 *
110
 * Disable interrupts and return previous
111
 * value of EFLAGS.
413 jermar 112
 *
113
 * @return Old interrupt priority level.
200 palkovsky 114
 */
413 jermar 115
static inline ipl_t interrupts_disable(void) {
116
    ipl_t v;
200 palkovsky 117
    __asm__ volatile (
118
        "pushfq\n"
119
        "popq %0\n"
120
        "cli\n"
121
        : "=r" (v)
122
        );
123
    return v;
124
}
125
 
413 jermar 126
/** Restore interrupt priority level.
200 palkovsky 127
 *
128
 * Restore EFLAGS.
413 jermar 129
 *
130
 * @param ipl Saved interrupt priority level.
200 palkovsky 131
 */
413 jermar 132
static inline void interrupts_restore(ipl_t ipl) {
200 palkovsky 133
    __asm__ volatile (
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        "pushq %0\n"
135
        "popfq\n"
413 jermar 136
        : : "r" (ipl)
200 palkovsky 137
        );
138
}
139
 
413 jermar 140
/** Return interrupt priority level.
206 palkovsky 141
 *
142
 * Return EFLAFS.
413 jermar 143
 *
144
 * @return Current interrupt priority level.
206 palkovsky 145
 */
413 jermar 146
static inline ipl_t interrupts_read(void) {
147
    ipl_t v;
206 palkovsky 148
    __asm__ volatile (
149
        "pushfq\n"
150
        "popq %0\n"
151
        : "=r" (v)
152
    );
153
    return v;
154
}
200 palkovsky 155
 
803 palkovsky 156
/** Write to MSR */
1780 jermar 157
static inline void write_msr(uint32_t msr, uint64_t value)
803 palkovsky 158
{
159
    __asm__ volatile (
160
        "wrmsr;" : : "c" (msr),
1780 jermar 161
        "a" ((uint32_t)(value)),
162
        "d" ((uint32_t)(value >> 32))
803 palkovsky 163
        );
164
}
219 palkovsky 165
 
1780 jermar 166
static inline unative_t read_msr(uint32_t msr)
803 palkovsky 167
{
1780 jermar 168
    uint32_t ax, dx;
803 palkovsky 169
 
170
    __asm__ volatile (
171
        "rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)
172
        );
1780 jermar 173
    return ((uint64_t)dx << 32) | ax;
803 palkovsky 174
}
175
 
176
 
268 palkovsky 177
/** Enable local APIC
178
 *
179
 * Enable local APIC in MSR.
180
 */
181
static inline void enable_l_apic_in_msr()
182
{
183
    __asm__ volatile (
348 jermar 184
        "movl $0x1b, %%ecx\n"
185
        "rdmsr\n"
186
        "orl $(1<<11),%%eax\n"
187
        "orl $(0xfee00000),%%eax\n"
188
        "wrmsr\n"
268 palkovsky 189
        :
190
        :
191
        :"%eax","%ecx","%edx"
192
        );
193
}
194
 
1780 jermar 195
static inline uintptr_t * get_ip()
581 palkovsky 196
{
1780 jermar 197
    uintptr_t *ip;
581 palkovsky 198
 
199
    __asm__ volatile (
200
        "mov %%rip, %0"
201
        : "=r" (ip)
202
        );
203
    return ip;
204
}
205
 
597 jermar 206
/** Invalidate TLB Entry.
207
 *
208
 * @param addr Address on a page whose TLB entry is to be invalidated.
209
 */
1780 jermar 210
static inline void invlpg(uintptr_t addr)
597 jermar 211
{
1780 jermar 212
    __asm__ volatile ("invlpg %0\n" :: "m" (*((unative_t *)addr)));
597 jermar 213
}
581 palkovsky 214
 
1186 jermar 215
/** Load GDTR register from memory.
216
 *
217
 * @param gdtr_reg Address of memory from where to load GDTR.
218
 */
219
static inline void gdtr_load(struct ptr_16_64 *gdtr_reg)
220
{
1251 jermar 221
    __asm__ volatile ("lgdtq %0\n" : : "m" (*gdtr_reg));
1186 jermar 222
}
223
 
224
/** Store GDTR register to memory.
225
 *
226
 * @param gdtr_reg Address of memory to where to load GDTR.
227
 */
228
static inline void gdtr_store(struct ptr_16_64 *gdtr_reg)
229
{
1251 jermar 230
    __asm__ volatile ("sgdtq %0\n" : : "m" (*gdtr_reg));
1186 jermar 231
}
232
 
233
/** Load IDTR register from memory.
234
 *
235
 * @param idtr_reg Address of memory from where to load IDTR.
236
 */
237
static inline void idtr_load(struct ptr_16_64 *idtr_reg)
238
{
1251 jermar 239
    __asm__ volatile ("lidtq %0\n" : : "m" (*idtr_reg));
1186 jermar 240
}
241
 
242
/** Load TR from descriptor table.
243
 *
244
 * @param sel Selector specifying descriptor of TSS segment.
245
 */
1780 jermar 246
static inline void tr_load(uint16_t sel)
1186 jermar 247
{
248
    __asm__ volatile ("ltr %0" : : "r" (sel));
249
}
250
 
1780 jermar 251
#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
1072 palkovsky 252
    { \
1780 jermar 253
    unative_t res; \
1072 palkovsky 254
    __asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \
255
    return res; \
256
    }
257
 
1780 jermar 258
#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
1072 palkovsky 259
    { \
260
    __asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \
261
    }
262
 
263
GEN_READ_REG(cr0);
264
GEN_READ_REG(cr2);
265
GEN_READ_REG(cr3);
266
GEN_WRITE_REG(cr3);
267
 
268
GEN_READ_REG(dr0);
269
GEN_READ_REG(dr1);
270
GEN_READ_REG(dr2);
271
GEN_READ_REG(dr3);
272
GEN_READ_REG(dr6);
273
GEN_READ_REG(dr7);
274
 
275
GEN_WRITE_REG(dr0);
276
GEN_WRITE_REG(dr1);
277
GEN_WRITE_REG(dr2);
278
GEN_WRITE_REG(dr3);
279
GEN_WRITE_REG(dr6);
280
GEN_WRITE_REG(dr7);
281
 
206 palkovsky 282
extern size_t interrupt_handler_size;
283
extern void interrupt_handlers(void);
284
 
173 jermar 285
#endif
1702 cejka 286
 
1888 jermar 287
/** @}
1702 cejka 288
 */