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1 jermar 1
/*
2071 jermar 2
 * Copyright (c) 2003-2004 Jakub Jermar
1 jermar 3
 * All rights reserved.
4
 *
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
7
 * are met:
8
 *
9
 * - Redistributions of source code must retain the above copyright
10
 *   notice, this list of conditions and the following disclaimer.
11
 * - Redistributions in binary form must reproduce the above copyright
12
 *   notice, this list of conditions and the following disclaimer in the
13
 *   documentation and/or other materials provided with the distribution.
14
 * - The name of the author may not be used to endorse or promote products
15
 *   derived from this software without specific prior written permission.
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
28
 
4153 mejdrech 29
/** @addtogroup mips32mm
1702 cejka 30
 * @{
31
 */
32
/** @file
33
 */
34
 
1 jermar 35
#include <arch/mm/tlb.h>
727 jermar 36
#include <mm/asid.h>
1 jermar 37
#include <mm/tlb.h>
391 jermar 38
#include <mm/page.h>
703 jermar 39
#include <mm/as.h>
1 jermar 40
#include <arch/cp0.h>
41
#include <panic.h>
42
#include <arch.h>
4153 mejdrech 43
#include <synch/mutex.h>
391 jermar 44
#include <print.h>
396 jermar 45
#include <debug.h>
983 palkovsky 46
#include <align.h>
1595 palkovsky 47
#include <interrupt.h>
4153 mejdrech 48
#include <symtab.h>
268 palkovsky 49
 
4153 mejdrech 50
static void tlb_refill_fail(istate_t *);
51
static void tlb_invalid_fail(istate_t *);
52
static void tlb_modified_fail(istate_t *);
391 jermar 53
 
4153 mejdrech 54
static pte_t *find_mapping_and_check(uintptr_t, int, istate_t *, int *);
399 jermar 55
 
4153 mejdrech 56
/** Initialize TLB.
391 jermar 57
 *
58
 * Invalidate all entries and mark wired entries.
59
 */
569 jermar 60
void tlb_arch_init(void)
389 jermar 61
{
599 jermar 62
    int i;
63
 
389 jermar 64
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
599 jermar 65
    cp0_entry_hi_write(0);
66
    cp0_entry_lo0_write(0);
67
    cp0_entry_lo1_write(0);
389 jermar 68
 
599 jermar 69
    /* Clear and initialize TLB. */
70
 
71
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
72
        cp0_index_write(i);
73
        tlbwi();
74
    }
598 jermar 75
 
389 jermar 76
    /*
77
     * The kernel is going to make use of some wired
391 jermar 78
     * entries (e.g. mapping kernel stacks in kseg3).
389 jermar 79
     */
80
    cp0_wired_write(TLB_WIRED);
81
}
82
 
4153 mejdrech 83
/** Process TLB Refill Exception.
391 jermar 84
 *
4153 mejdrech 85
 * @param istate    Interrupted register context.
391 jermar 86
 */
958 jermar 87
void tlb_refill(istate_t *istate)
1 jermar 88
{
396 jermar 89
    entry_lo_t lo;
1044 jermar 90
    entry_hi_t hi;
91
    asid_t asid;
1780 jermar 92
    uintptr_t badvaddr;
391 jermar 93
    pte_t *pte;
1288 jermar 94
    int pfrc;
4153 mejdrech 95
 
391 jermar 96
    badvaddr = cp0_badvaddr_read();
4153 mejdrech 97
 
98
    mutex_lock(&AS->lock);
1044 jermar 99
    asid = AS->asid;
4153 mejdrech 100
    mutex_unlock(&AS->lock);
101
 
1044 jermar 102
    page_table_lock(AS, true);
4153 mejdrech 103
 
1411 jermar 104
    pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
1288 jermar 105
    if (!pte) {
106
        switch (pfrc) {
107
        case AS_PF_FAULT:
108
            goto fail;
109
            break;
110
        case AS_PF_DEFER:
111
            /*
112
             * The page fault came during copy_from_uspace()
113
             * or copy_to_uspace().
114
             */
115
            page_table_unlock(AS, true);
116
            return;
117
        default:
4153 mejdrech 118
            panic("Unexpected pfrc (%d).", pfrc);
1288 jermar 119
        }
120
    }
391 jermar 121
 
122
    /*
394 jermar 123
     * Record access to PTE.
391 jermar 124
     */
394 jermar 125
    pte->a = 1;
391 jermar 126
 
3228 decky 127
    tlb_prepare_entry_hi(&hi, asid, badvaddr);
4153 mejdrech 128
    tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,
129
        pte->pfn);
394 jermar 130
 
391 jermar 131
    /*
132
     * New entry is to be inserted into TLB
133
     */
399 jermar 134
    cp0_entry_hi_write(hi.value);
4153 mejdrech 135
    if ((badvaddr / PAGE_SIZE) % 2 == 0) {
396 jermar 136
        cp0_entry_lo0_write(lo.value);
391 jermar 137
        cp0_entry_lo1_write(0);
138
    }
139
    else {
140
        cp0_entry_lo0_write(0);
396 jermar 141
        cp0_entry_lo1_write(lo.value);
391 jermar 142
    }
612 jermar 143
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
391 jermar 144
    tlbwr();
145
 
1044 jermar 146
    page_table_unlock(AS, true);
391 jermar 147
    return;
148
 
149
fail:
1044 jermar 150
    page_table_unlock(AS, true);
958 jermar 151
    tlb_refill_fail(istate);
391 jermar 152
}
153
 
4153 mejdrech 154
/** Process TLB Invalid Exception.
394 jermar 155
 *
4153 mejdrech 156
 * @param istate    Interrupted register context.
394 jermar 157
 */
958 jermar 158
void tlb_invalid(istate_t *istate)
391 jermar 159
{
396 jermar 160
    tlb_index_t index;
1780 jermar 161
    uintptr_t badvaddr;
396 jermar 162
    entry_lo_t lo;
399 jermar 163
    entry_hi_t hi;
394 jermar 164
    pte_t *pte;
1288 jermar 165
    int pfrc;
394 jermar 166
 
167
    badvaddr = cp0_badvaddr_read();
168
 
169
    /*
170
     * Locate the faulting entry in TLB.
171
     */
399 jermar 172
    hi.value = cp0_entry_hi_read();
3228 decky 173
    tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
399 jermar 174
    cp0_entry_hi_write(hi.value);
394 jermar 175
    tlbp();
396 jermar 176
    index.value = cp0_index_read();
1044 jermar 177
 
178
    page_table_lock(AS, true); 
394 jermar 179
 
180
    /*
181
     * Fail if the entry is not in TLB.
182
     */
396 jermar 183
    if (index.p) {
184
        printf("TLB entry not found.\n");
394 jermar 185
        goto fail;
396 jermar 186
    }
394 jermar 187
 
1411 jermar 188
    pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
1288 jermar 189
    if (!pte) {
190
        switch (pfrc) {
191
        case AS_PF_FAULT:
192
            goto fail;
193
            break;
194
        case AS_PF_DEFER:
195
            /*
196
             * The page fault came during copy_from_uspace()
197
             * or copy_to_uspace().
198
             */
199
            page_table_unlock(AS, true);             
200
            return;
201
        default:
4153 mejdrech 202
            panic("Unexpected pfrc (%d).", pfrc);
1288 jermar 203
        }
204
    }
394 jermar 205
 
206
    /*
207
     * Read the faulting TLB entry.
208
     */
209
    tlbr();
210
 
211
    /*
212
     * Record access to PTE.
213
     */
214
    pte->a = 1;
215
 
4153 mejdrech 216
    tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,
217
        pte->pfn);
394 jermar 218
 
219
    /*
220
     * The entry is to be updated in TLB.
221
     */
4153 mejdrech 222
    if ((badvaddr / PAGE_SIZE) % 2 == 0)
396 jermar 223
        cp0_entry_lo0_write(lo.value);
394 jermar 224
    else
396 jermar 225
        cp0_entry_lo1_write(lo.value);
612 jermar 226
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
394 jermar 227
    tlbwi();
228
 
1044 jermar 229
    page_table_unlock(AS, true);
394 jermar 230
    return;
231
 
232
fail:
1044 jermar 233
    page_table_unlock(AS, true);
958 jermar 234
    tlb_invalid_fail(istate);
391 jermar 235
}
236
 
4153 mejdrech 237
/** Process TLB Modified Exception.
394 jermar 238
 *
4153 mejdrech 239
 * @param istate    Interrupted register context.
394 jermar 240
 */
958 jermar 241
void tlb_modified(istate_t *istate)
391 jermar 242
{
396 jermar 243
    tlb_index_t index;
1780 jermar 244
    uintptr_t badvaddr;
396 jermar 245
    entry_lo_t lo;
399 jermar 246
    entry_hi_t hi;
394 jermar 247
    pte_t *pte;
1288 jermar 248
    int pfrc;
394 jermar 249
 
250
    badvaddr = cp0_badvaddr_read();
251
 
252
    /*
253
     * Locate the faulting entry in TLB.
254
     */
399 jermar 255
    hi.value = cp0_entry_hi_read();
3228 decky 256
    tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
399 jermar 257
    cp0_entry_hi_write(hi.value);
394 jermar 258
    tlbp();
396 jermar 259
    index.value = cp0_index_read();
1044 jermar 260
 
261
    page_table_lock(AS, true); 
394 jermar 262
 
263
    /*
264
     * Fail if the entry is not in TLB.
265
     */
396 jermar 266
    if (index.p) {
267
        printf("TLB entry not found.\n");
394 jermar 268
        goto fail;
396 jermar 269
    }
394 jermar 270
 
1411 jermar 271
    pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc);
1288 jermar 272
    if (!pte) {
273
        switch (pfrc) {
274
        case AS_PF_FAULT:
275
            goto fail;
276
            break;
277
        case AS_PF_DEFER:
278
            /*
279
             * The page fault came during copy_from_uspace()
280
             * or copy_to_uspace().
281
             */
282
            page_table_unlock(AS, true);             
283
            return;
284
        default:
4153 mejdrech 285
            panic("Unexpected pfrc (%d).", pfrc);
1288 jermar 286
        }
287
    }
394 jermar 288
 
289
    /*
290
     * Read the faulting TLB entry.
291
     */
292
    tlbr();
293
 
294
    /*
295
     * Record access and write to PTE.
296
     */
297
    pte->a = 1;
831 jermar 298
    pte->d = 1;
394 jermar 299
 
4153 mejdrech 300
    tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable,
301
        pte->pfn);
394 jermar 302
 
303
    /*
304
     * The entry is to be updated in TLB.
305
     */
4153 mejdrech 306
    if ((badvaddr / PAGE_SIZE) % 2 == 0)
396 jermar 307
        cp0_entry_lo0_write(lo.value);
394 jermar 308
    else
396 jermar 309
        cp0_entry_lo1_write(lo.value);
612 jermar 310
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
394 jermar 311
    tlbwi();
312
 
1044 jermar 313
    page_table_unlock(AS, true);
394 jermar 314
    return;
315
 
316
fail:
1044 jermar 317
    page_table_unlock(AS, true);
958 jermar 318
    tlb_modified_fail(istate);
391 jermar 319
}
320
 
958 jermar 321
void tlb_refill_fail(istate_t *istate)
391 jermar 322
{
4153 mejdrech 323
    char *symbol, *sym2;
324 palkovsky 324
 
4153 mejdrech 325
    symbol = symtab_fmt_name_lookup(istate->epc);
326
    sym2 = symtab_fmt_name_lookup(istate->ra);
327
 
328
    fault_if_from_uspace(istate, "TLB Refill Exception on %p.",
329
        cp0_badvaddr_read());
330
    panic("%x: TLB Refill Exception at %x (%s<-%s).", cp0_badvaddr_read(),
331
        istate->epc, symbol, sym2);
1 jermar 332
}
333
 
391 jermar 334
 
958 jermar 335
void tlb_invalid_fail(istate_t *istate)
1 jermar 336
{
4153 mejdrech 337
    char *symbol;
268 palkovsky 338
 
4153 mejdrech 339
    symbol = symtab_fmt_name_lookup(istate->epc);
340
 
341
    fault_if_from_uspace(istate, "TLB Invalid Exception on %p.",
342
        cp0_badvaddr_read());
343
    panic("%x: TLB Invalid Exception at %x (%s).", cp0_badvaddr_read(),
344
        istate->epc, symbol);
1 jermar 345
}
346
 
958 jermar 347
void tlb_modified_fail(istate_t *istate)
389 jermar 348
{
4153 mejdrech 349
    char *symbol;
389 jermar 350
 
4153 mejdrech 351
    symbol = symtab_fmt_name_lookup(istate->epc);
352
 
353
    fault_if_from_uspace(istate, "TLB Modified Exception on %p.",
354
        cp0_badvaddr_read());
355
    panic("%x: TLB Modified Exception at %x (%s).", cp0_badvaddr_read(),
356
        istate->epc, symbol);
389 jermar 357
}
358
 
4153 mejdrech 359
/** Try to find PTE for faulting address.
394 jermar 360
 *
703 jermar 361
 * The AS->lock must be held on entry to this function.
394 jermar 362
 *
4153 mejdrech 363
 * @param badvaddr  Faulting virtual address.
364
 * @param access    Access mode that caused the fault.
365
 * @param istate    Pointer to interrupted state.
366
 * @param pfrc      Pointer to variable where as_page_fault() return code
367
 *          will be stored.
394 jermar 368
 *
4153 mejdrech 369
 * @return      PTE on success, NULL otherwise.
394 jermar 370
 */
4153 mejdrech 371
pte_t *
372
find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate,
373
    int *pfrc)
394 jermar 374
{
396 jermar 375
    entry_hi_t hi;
394 jermar 376
    pte_t *pte;
377
 
396 jermar 378
    hi.value = cp0_entry_hi_read();
394 jermar 379
 
380
    /*
381
     * Handler cannot succeed if the ASIDs don't match.
382
     */
703 jermar 383
    if (hi.asid != AS->asid) {
384
        printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);
394 jermar 385
        return NULL;
396 jermar 386
    }
703 jermar 387
 
394 jermar 388
    /*
703 jermar 389
     * Check if the mapping exists in page tables.
390
     */
756 jermar 391
    pte = page_mapping_find(AS, badvaddr);
4153 mejdrech 392
    if (pte && pte->p && (pte->w || access != PF_ACCESS_WRITE)) {
703 jermar 393
        /*
394
         * Mapping found in page tables.
395
         * Immediately succeed.
396
         */
397
        return pte;
398
    } else {
1288 jermar 399
        int rc;
400
 
703 jermar 401
        /*
402
         * Mapping not found in page tables.
403
         * Resort to higher-level page fault handler.
404
         */
1044 jermar 405
        page_table_unlock(AS, true);
1411 jermar 406
        switch (rc = as_page_fault(badvaddr, access, istate)) {
1288 jermar 407
        case AS_PF_OK:
703 jermar 408
            /*
409
             * The higher-level page fault handler succeeded,
410
             * The mapping ought to be in place.
411
             */
1044 jermar 412
            page_table_lock(AS, true);
756 jermar 413
            pte = page_mapping_find(AS, badvaddr);
831 jermar 414
            ASSERT(pte && pte->p);
4153 mejdrech 415
            ASSERT(pte->w || access != PF_ACCESS_WRITE);
703 jermar 416
            return pte;
1288 jermar 417
            break;
418
        case AS_PF_DEFER:
1044 jermar 419
            page_table_lock(AS, true);
1288 jermar 420
            *pfrc = AS_PF_DEFER;
421
            return NULL;
422
            break;
423
        case AS_PF_FAULT:
424
            page_table_lock(AS, true);
425
            *pfrc = AS_PF_FAULT;
1044 jermar 426
            return NULL;
1288 jermar 427
            break;
428
        default:
4153 mejdrech 429
            panic("Unexpected rc (%d).", rc);
703 jermar 430
        }
1044 jermar 431
 
703 jermar 432
    }
394 jermar 433
}
434
 
4153 mejdrech 435
void
436
tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable,
437
    uintptr_t pfn)
394 jermar 438
{
399 jermar 439
    lo->value = 0;
394 jermar 440
    lo->g = g;
441
    lo->v = v;
442
    lo->d = d;
831 jermar 443
    lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
394 jermar 444
    lo->pfn = pfn;
445
}
399 jermar 446
 
3228 decky 447
void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr)
399 jermar 448
{
983 palkovsky 449
    hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);
399 jermar 450
    hi->asid = asid;
451
}
569 jermar 452
 
594 jermar 453
/** Print contents of TLB. */
569 jermar 454
void tlb_print(void)
455
{
612 jermar 456
    page_mask_t mask;
594 jermar 457
    entry_lo_t lo0, lo1;
704 jermar 458
    entry_hi_t hi, hi_save;
2720 decky 459
    unsigned int i;
594 jermar 460
 
704 jermar 461
    hi_save.value = cp0_entry_hi_read();
2720 decky 462
 
463
    printf("#  ASID VPN2   MASK G V D C PFN\n");
464
    printf("-- ---- ------ ---- - - - - ------\n");
465
 
594 jermar 466
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
467
        cp0_index_write(i);
468
        tlbr();
469
 
612 jermar 470
        mask.value = cp0_pagemask_read();
594 jermar 471
        hi.value = cp0_entry_hi_read();
472
        lo0.value = cp0_entry_lo0_read();
473
        lo1.value = cp0_entry_lo1_read();
474
 
2720 decky 475
        printf("%-2u %-4u %#6x %#4x %1u %1u %1u %1u %#6x\n",
4153 mejdrech 476
            i, hi.asid, hi.vpn2, mask.mask,
477
            lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn);
2720 decky 478
        printf("                    %1u %1u %1u %1u %#6x\n",
4153 mejdrech 479
            lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
594 jermar 480
    }
704 jermar 481
 
482
    cp0_entry_hi_write(hi_save.value);
569 jermar 483
}
598 jermar 484
 
618 jermar 485
/** Invalidate all not wired TLB entries. */
598 jermar 486
void tlb_invalidate_all(void)
487
{
599 jermar 488
    ipl_t ipl;
489
    entry_lo_t lo0, lo1;
704 jermar 490
    entry_hi_t hi_save;
598 jermar 491
    int i;
492
 
704 jermar 493
    hi_save.value = cp0_entry_hi_read();
599 jermar 494
    ipl = interrupts_disable();
598 jermar 495
 
618 jermar 496
    for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) {
598 jermar 497
        cp0_index_write(i);
599 jermar 498
        tlbr();
499
 
500
        lo0.value = cp0_entry_lo0_read();
501
        lo1.value = cp0_entry_lo1_read();
502
 
503
        lo0.v = 0;
504
        lo1.v = 0;
505
 
506
        cp0_entry_lo0_write(lo0.value);
507
        cp0_entry_lo1_write(lo1.value);
508
 
598 jermar 509
        tlbwi();
510
    }
599 jermar 511
 
512
    interrupts_restore(ipl);
704 jermar 513
    cp0_entry_hi_write(hi_save.value);
598 jermar 514
}
515
 
516
/** Invalidate all TLB entries belonging to specified address space.
517
 *
518
 * @param asid Address space identifier.
519
 */
520
void tlb_invalidate_asid(asid_t asid)
521
{
599 jermar 522
    ipl_t ipl;
523
    entry_lo_t lo0, lo1;
704 jermar 524
    entry_hi_t hi, hi_save;
598 jermar 525
    int i;
526
 
599 jermar 527
    ASSERT(asid != ASID_INVALID);
528
 
704 jermar 529
    hi_save.value = cp0_entry_hi_read();
599 jermar 530
    ipl = interrupts_disable();
531
 
598 jermar 532
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
533
        cp0_index_write(i);
534
        tlbr();
535
 
599 jermar 536
        hi.value = cp0_entry_hi_read();
537
 
598 jermar 538
        if (hi.asid == asid) {
599 jermar 539
            lo0.value = cp0_entry_lo0_read();
540
            lo1.value = cp0_entry_lo1_read();
541
 
542
            lo0.v = 0;
543
            lo1.v = 0;
544
 
545
            cp0_entry_lo0_write(lo0.value);
546
            cp0_entry_lo1_write(lo1.value);
547
 
598 jermar 548
            tlbwi();
549
        }
550
    }
599 jermar 551
 
552
    interrupts_restore(ipl);
704 jermar 553
    cp0_entry_hi_write(hi_save.value);
598 jermar 554
}
555
 
4153 mejdrech 556
/** Invalidate TLB entries for specified page range belonging to specified
557
 * address space.
598 jermar 558
 *
4153 mejdrech 559
 * @param asid      Address space identifier.
560
 * @param page      First page whose TLB entry is to be invalidated.
561
 * @param cnt       Number of entries to invalidate.
598 jermar 562
 */
4581 mejdrech 563
void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt)
598 jermar 564
{
2745 decky 565
    unsigned int i;
599 jermar 566
    ipl_t ipl;
567
    entry_lo_t lo0, lo1;
704 jermar 568
    entry_hi_t hi, hi_save;
598 jermar 569
    tlb_index_t index;
570
 
599 jermar 571
    ASSERT(asid != ASID_INVALID);
572
 
704 jermar 573
    hi_save.value = cp0_entry_hi_read();
599 jermar 574
    ipl = interrupts_disable();
575
 
2745 decky 576
    for (i = 0; i < cnt + 1; i += 2) {
727 jermar 577
        hi.value = 0;
3228 decky 578
        tlb_prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE);
727 jermar 579
        cp0_entry_hi_write(hi.value);
599 jermar 580
 
727 jermar 581
        tlbp();
582
        index.value = cp0_index_read();
598 jermar 583
 
727 jermar 584
        if (!index.p) {
4153 mejdrech 585
            /*
586
             * Entry was found, index register contains valid
587
             * index.
588
             */
727 jermar 589
            tlbr();
599 jermar 590
 
727 jermar 591
            lo0.value = cp0_entry_lo0_read();
592
            lo1.value = cp0_entry_lo1_read();
599 jermar 593
 
727 jermar 594
            lo0.v = 0;
595
            lo1.v = 0;
599 jermar 596
 
727 jermar 597
            cp0_entry_lo0_write(lo0.value);
598
            cp0_entry_lo1_write(lo1.value);
599 jermar 599
 
727 jermar 600
            tlbwi();
601
        }
598 jermar 602
    }
599 jermar 603
 
604
    interrupts_restore(ipl);
704 jermar 605
    cp0_entry_hi_write(hi_save.value);
598 jermar 606
}
1702 cejka 607
 
1776 jermar 608
/** @}
1702 cejka 609
 */