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1 jermar 1
/*
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 * Copyright (c) 2003-2004 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup mips32mm
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 * @{
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 */
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/** @file
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 */
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#ifndef KERN_mips32_TLB_H_
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#define KERN_mips32_TLB_H_
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#include <arch/types.h>
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#include <typedefs.h>
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#include <arch/mm/asid.h>
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#include <arch/exception.h>
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#define TLB_ENTRY_COUNT  48
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#define TLB_WIRED               1
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#define TLB_KSTACK_WIRED_INDEX  0
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#define TLB_PAGE_MASK_4K    (0x000 << 13)
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#define TLB_PAGE_MASK_16K   (0x003 << 13)
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#define TLB_PAGE_MASK_64K   (0x00f << 13)
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#define TLB_PAGE_MASK_256K  (0x03f << 13)
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#define TLB_PAGE_MASK_1M    (0x0ff << 13)
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#define TLB_PAGE_MASK_4M    (0x3ff << 13)
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#define TLB_PAGE_MASK_16M   (0xfff << 13)
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#define PAGE_UNCACHED             2
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#define PAGE_CACHEABLE_EXC_WRITE  5
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typedef union {
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    struct {
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#ifdef BIG_ENDIAN
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        unsigned : 2;       /* zero */
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        unsigned pfn : 24;  /* frame number */
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        unsigned c : 3;     /* cache coherency attribute */
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        unsigned d : 1;     /* dirty/write-protect bit */
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        unsigned v : 1;     /* valid bit */
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        unsigned g : 1;     /* global bit */
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#else
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        unsigned g : 1;     /* global bit */
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        unsigned v : 1;     /* valid bit */
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        unsigned d : 1;     /* dirty/write-protect bit */
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        unsigned c : 3;     /* cache coherency attribute */
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        unsigned pfn : 24;  /* frame number */
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        unsigned : 2;       /* zero */
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#endif
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    } __attribute__ ((packed));
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    uint32_t value;
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} entry_lo_t;
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typedef union {
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    struct {
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#ifdef BIG_ENDIAN
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        unsigned vpn2 : 19;
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        unsigned : 5;
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        unsigned asid : 8;
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#else
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        unsigned asid : 8;
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        unsigned : 5;
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        unsigned vpn2 : 19;
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#endif
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    } __attribute__ ((packed));
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    uint32_t value;
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} entry_hi_t;
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typedef union {
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    struct {
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#ifdef BIG_ENDIAN
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        unsigned : 7;
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        unsigned mask : 12;
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        unsigned : 13;
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#else
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        unsigned : 13;
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        unsigned mask : 12;
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        unsigned : 7;
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#endif
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    } __attribute__ ((packed));
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    uint32_t value;
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} page_mask_t;
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typedef union {
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    struct {
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#ifdef BIG_ENDIAN
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        unsigned p : 1;
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        unsigned : 27;
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        unsigned index : 4;
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#else
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        unsigned index : 4;
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        unsigned : 27;
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        unsigned p : 1;
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#endif
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    } __attribute__ ((packed));
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    uint32_t value;
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} tlb_index_t;
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/** Probe TLB for Matching Entry
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 *
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 * Probe TLB for Matching Entry.
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 */
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static inline void tlbp(void)
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{
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    asm volatile ("tlbp\n\t");
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}
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/** Read Indexed TLB Entry
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 *
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 * Read Indexed TLB Entry.
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 */
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static inline void tlbr(void)
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{
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    asm volatile ("tlbr\n\t");
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}
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/** Write Indexed TLB Entry
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 *
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 * Write Indexed TLB Entry.
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 */
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static inline void tlbwi(void)
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{
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    asm volatile ("tlbwi\n\t");
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}
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/** Write Random TLB Entry
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 *
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 * Write Random TLB Entry.
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 */
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static inline void tlbwr(void)
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{
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    asm volatile ("tlbwr\n\t");
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}
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#define tlb_invalidate(asid)  tlb_invalidate_asid(asid)
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extern void tlb_invalid(istate_t *istate);
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extern void tlb_refill(istate_t *istate);
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extern void tlb_modified(istate_t *istate);
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extern void tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn);
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extern void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr);
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#endif
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/** @}
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 */