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212 vana 1
#
2
# Copyright (C) 2005 Jakub Vana
478 jermar 3
# Copyright (C) 2005 Jakub Jermar
212 vana 4
# All rights reserved.
5
#
6
# Redistribution and use in source and binary forms, with or without
7
# modification, are permitted provided that the following conditions
8
# are met:
9
#
10
# - Redistributions of source code must retain the above copyright
11
#   notice, this list of conditions and the following disclaimer.
12
# - Redistributions in binary form must reproduce the above copyright
13
#   notice, this list of conditions and the following disclaimer in the
14
#   documentation and/or other materials provided with the distribution.
15
# - The name of the author may not be used to endorse or promote products
16
#   derived from this software without specific prior written permission.
17
#
18
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28
#
29
 
443 jermar 30
#include <arch/stack.h>
478 jermar 31
#include <arch/register.h>
912 jermar 32
#include <arch/mm/page.h>
33
#include <align.h>
212 vana 34
 
962 jermar 35
#define STACK_ITEMS		19
912 jermar 36
#define STACK_FRAME_SIZE	ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)
443 jermar 37
 
912 jermar 38
#if (STACK_ITEMS % 2 == 0)
39
#	define STACK_FRAME_BIAS	8
40
#else
41
#	define STACK_FRAME_BIAS 16
443 jermar 42
#endif
43
 
911 jermar 44
/** Partitioning of bank 0 registers. */
45
#define R_OFFS 		r16
46
#define R_HANDLER	r17
47
#define R_RET		r18
921 jermar 48
#define R_TMP		r19
916 jermar 49
#define R_KSTACK_BSP	r22	/* keep in sync with before_thread_runs_arch() */
911 jermar 50
#define R_KSTACK	r23	/* keep in sync with before_thread_runs_arch() */
51
 
438 jermar 52
/** Heavyweight interrupt handler
53
 *
435 jermar 54
 * This macro roughly follows steps from 1 to 19 described in
55
 * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
56
 *
438 jermar 57
 * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
58
 * This goal is achieved by using procedure calls after RSE becomes operational.
59
 *
435 jermar 60
 * Some steps are skipped (enabling and disabling interrupts).
916 jermar 61
 * Some steps are not fully supported yet (e.g. dealing with floating-point
62
 * context).
456 jermar 63
 *
64
 * @param offs Offset from the beginning of IVT.
65
 * @param handler Interrupt handler address.
435 jermar 66
 */
470 jermar 67
.macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler
68
    .org ivt + \offs
911 jermar 69
	mov R_OFFS = \offs
70
	movl R_HANDLER = \handler ;;
470 jermar 71
	br heavyweight_handler
72
.endm
212 vana 73
 
470 jermar 74
.global heavyweight_handler
75
heavyweight_handler:
435 jermar 76
    /* 1. copy interrupt registers into bank 0 */
911 jermar 77
 
78
	/*
912 jermar 79
	 * Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0.
911 jermar 80
	 */
435 jermar 81
	mov r24 = cr.iip
82
	mov r25 = cr.ipsr
83
	mov r26 = cr.iipa
84
	mov r27 = cr.isr
85
	mov r28 = cr.ifa
86
 
87
    /* 2. preserve predicate register into bank 0 */
88
	mov r29 = pr ;;
89
 
438 jermar 90
    /* 3. switch to kernel memory stack */
912 jermar 91
    	mov r30 = cr.ipsr
916 jermar 92
	shr.u r31 = r12, VRN_SHIFT ;;
912 jermar 93
 
916 jermar 94
	shr.u r30 = r30, PSR_CPL_SHIFT ;;
95
	and r30 = PSR_CPL_MASK_SHIFTED, r30 ;;
96
 
912 jermar 97
	/*
916 jermar 98
	 * Set p3 to true if the interrupted context executed in kernel mode.
99
	 * Set p4 to false if the interrupted context didn't execute in kernel mode.
912 jermar 100
	 */
916 jermar 101
	cmp.eq p3, p4 = r30, r0 ;;
102
	cmp.eq p1, p2 = r30, r0 ;;	/* remember IPSR setting in p1 and p2 */
912 jermar 103
 
104
	/*
916 jermar 105
	 * Set p3 to true if the stack register references kernel address space.
106
	 * Set p4 to false if the stack register doesn't reference kernel address space.
912 jermar 107
	 */
921 jermar 108
(p3)	cmp.eq p3, p4 = VRN_KERNEL, r31 ;;
912 jermar 109
 
110
	/*
916 jermar 111
	 * Now, p4 is true iff the stack needs to be switched to kernel stack.
912 jermar 112
	 */
113
	mov r30 = r12
921 jermar 114
(p4)	mov r12 = R_KSTACK ;;
912 jermar 115
 
116
	add r31 = -STACK_FRAME_BIAS, r12 ;;
470 jermar 117
	add r12 = -STACK_FRAME_SIZE, r12
118
 
921 jermar 119
    /* 4. save registers in bank 0 into memory stack */
120
 
121
	/*
122
	 * If this is break_instruction handler,
123
	 * copy input parameters to stack.
124
	 */
125
    	mov R_TMP = 0x2c00 ;;
126
	cmp.eq p6,p5 = R_OFFS, R_TMP ;;
127
 
128
	/*
129
	 * From now on, if this is break_instruction handler, p6 is true and p5 is false.
130
	 * Otherwise p6 is false and p5 is true.
131
	 * Note that p5 is a preserved predicate register and we make use of it.
132
	 */
962 jermar 133
 
134
(p6)	st8 [r31] = r36, -8 ;;		/* save in4 */	
921 jermar 135
(p6)	st8 [r31] = r35, -8 ;;		/* save in3 */
136
(p6) 	st8 [r31] = r34, -8 ;;		/* save in2 */
137
(p6)	st8 [r31] = r33, -8 ;;		/* save in1 */
138
(p6)	st8 [r31] = r32, -8 ;;		/* save in0 */
962 jermar 139
(p5)	add r31 = -40, r31 ;;
921 jermar 140
 
912 jermar 141
	st8 [r31] = r30, -8 ;;		/* save old stack pointer */ 
142
 
143
	st8 [r31] = r29, -8 ;;		/* save predicate registers */
438 jermar 144
 
912 jermar 145
	st8 [r31] = r24, -8 ;;		/* save cr.iip */
146
	st8 [r31] = r25, -8 ;;		/* save cr.ipsr */
147
	st8 [r31] = r26, -8 ;;		/* save cr.iipa */
148
	st8 [r31] = r27, -8 ;;		/* save cr.isr */
149
	st8 [r31] = r28, -8 ;;		/* save cr.ifa */
438 jermar 150
 
151
    /* 5. RSE switch from interrupted context */
435 jermar 152
	mov r24 = ar.rsc
153
	mov r25 = ar.pfs
154
	cover
155
	mov r26 = cr.ifs
156
 
916 jermar 157
	st8 [r31] = r24, -8 ;;		/* save ar.rsc */
158
	st8 [r31] = r25, -8 ;;		/* save ar.pfs */
159
	st8 [r31] = r26, -8		/* save ar.ifs */
435 jermar 160
 
919 jermar 161
	and r24 = ~(RSC_PL_MASK), r24 ;;
162
	and r30 = ~(RSC_MODE_MASK), r24 ;;
163
	mov ar.rsc = r30 ;;		/* update RSE state */
435 jermar 164
 
165
	mov r27 = ar.rnat
470 jermar 166
	mov r28 = ar.bspstore ;;
435 jermar 167
 
916 jermar 168
	/*
169
	 * Inspect BSPSTORE to figure out whether it is necessary to switch to kernel BSPSTORE.
170
	 */
921 jermar 171
(p1)	shr.u r30 = r28, VRN_SHIFT ;;
172
(p1)	cmp.eq p1, p2 = VRN_KERNEL, r30 ;;
435 jermar 173
 
916 jermar 174
	/*
175
	 * If BSPSTORE needs to be switched, p1 is false and p2 is true.
176
	 */
921 jermar 177
(p1)	mov r30 = r28
178
(p2)	mov r30 = R_KSTACK_BSP ;;
179
(p2)	mov ar.bspstore = r30 ;;
916 jermar 180
 
435 jermar 181
	mov r29 = ar.bsp
182
 
916 jermar 183
	st8 [r31] = r27, -8 ;;		/* save ar.rnat */
184
	st8 [r31] = r30, -8 ;;		/* save new value written to ar.bspstore */
185
	st8 [r31] = r28, -8 ;;		/* save ar.bspstore */
186
	st8 [r31] = r29, -8 		/* save ar.bsp */
435 jermar 187
 
919 jermar 188
	mov ar.rsc = r24		/* restore RSE's setting + kernel privileges */
435 jermar 189
 
470 jermar 190
    /* steps 6 - 15 are done by heavyweight_handler_inner() */
916 jermar 191
	mov R_RET = b0 			/* save b0 belonging to interrupted context */
911 jermar 192
	br.call.sptk.many b0 = heavyweight_handler_inner
916 jermar 193
0:	mov b0 = R_RET			/* restore b0 belonging to the interrupted context */
438 jermar 194
 
470 jermar 195
    /* 16. RSE switch to interrupted context */
916 jermar 196
	cover				/* allocate zerro size frame (step 1 (from Intel Docs)) */
438 jermar 197
 
470 jermar 198
	add r31 = STACK_SCRATCH_AREA_SIZE, r12 ;;
199
 
915 jermar 200
	ld8 r30 = [r31], +8 ;;		/* load ar.bsp */
201
	ld8 r29 = [r31], +8 ;;   	/* load ar.bspstore */
202
	ld8 r28 = [r31], +8 ;;   	/* load ar.bspstore_new */
203
	sub r27 = r30 , r28 ;;		/* calculate loadrs (step 2) */
470 jermar 204
	shl r27 = r27, 16
205
 
206
	mov r24 = ar.rsc ;;
207
	and r30 = ~3, r24 ;;
208
	or  r24 = r30 , r27 ;;     
209
	mov ar.rsc = r24 ;;		/* place RSE in enforced lazy mode */
210
 
211
	loadrs 				/* (step 3) */
212
 
213
	ld8 r27 = [r31], +8 ;;		/* load ar.rnat */
214
	ld8 r26 = [r31], +8 ;;		/* load cr.ifs */
215
	ld8 r25 = [r31], +8 ;;		/* load ar.pfs */
216
	ld8 r24 = [r31], +8 ;;		/* load ar.rsc */
217
 
915 jermar 218
	mov ar.bspstore = r29 ;;	/* (step 4) */
219
	mov ar.rnat = r27		/* (step 5) */
470 jermar 220
 
221
	mov ar.pfs = r25		/* (step 6) */
222
	mov cr.ifs = r26	
223
 
224
	mov ar.rsc = r24		/* (step 7) */
225
 
226
    /* 17. restore interruption state from memory stack */
916 jermar 227
	ld8 r28 = [r31], +8 ;;		/* load cr.ifa */		
228
	ld8 r27 = [r31], +8 ;;		/* load cr.isr */
229
	ld8 r26 = [r31], +8 ;;		/* load cr.iipa */
230
	ld8 r25 = [r31], +8 ;;		/* load cr.ipsr */
231
	ld8 r24 = [r31], +8 ;;		/* load cr.iip */
470 jermar 232
 
233
	mov cr.iip = r24
234
	mov cr.ipsr = r25
235
	mov cr.iipa = r26
236
	mov cr.isr = r27
237
	mov cr.ifa = r28
238
 
239
    /* 18. restore predicate registers from memory stack */
916 jermar 240
	ld8 r29 = [r31], +8 ;;		/* load predicate registers */
470 jermar 241
	mov pr = r29
242
 
243
    /* 19. return from interruption */
916 jermar 244
    	ld8 r12 = [r31]			/* load stack pointer */ 
470 jermar 245
	rfi ;;
246
 
438 jermar 247
.global heavyweight_handler_inner
248
heavyweight_handler_inner:
249
	/*
250
	 * From this point, the rest of the interrupted context
251
	 * will be preserved in stacked registers and backing store.
252
	 */
979 vana 253
	alloc loc0 = ar.pfs, 0, 48, 2, 0 ;;
438 jermar 254
 
470 jermar 255
	/* bank 0 is going to be shadowed, copy essential data from there */
911 jermar 256
	mov loc1 = R_RET	/* b0 belonging to interrupted context */
257
	mov loc2 = R_HANDLER
258
	mov out0 = R_OFFS
470 jermar 259
 
260
	add out1 = STACK_SCRATCH_AREA_SIZE, r12
438 jermar 261
 
435 jermar 262
    /* 6. switch to bank 1 and reenable PSR.ic */
478 jermar 263
	ssm PSR_IC_MASK
435 jermar 264
	bsw.1 ;;
265
	srlz.d
266
 
267
    /* 7. preserve branch and application registers */
470 jermar 268
    	mov loc3 = ar.unat
269
	mov loc4 = ar.lc
270
	mov loc5 = ar.ec
271
	mov loc6 = ar.ccv
272
	mov loc7 = ar.csd
273
	mov loc8 = ar.ssd
435 jermar 274
 
470 jermar 275
	mov loc9 = b0
276
	mov loc10 = b1
277
	mov loc11 = b2
278
	mov loc12 = b3
279
	mov loc13 = b4
280
	mov loc14 = b5
281
	mov loc15 = b6
282
	mov loc16 = b7
438 jermar 283
 
435 jermar 284
    /* 8. preserve general and floating-point registers */
285
	/* TODO: save floating-point context */
470 jermar 286
	mov loc17 = r1
287
	mov loc18 = r2
288
	mov loc19 = r3
289
	mov loc20 = r4
290
	mov loc21 = r5
291
	mov loc22 = r6
292
	mov loc23 = r7
921 jermar 293
(p5)	mov loc24 = r8		/* only if not in break_instruction handler */
470 jermar 294
	mov loc25 = r9
295
	mov loc26 = r10
296
	mov loc27 = r11
438 jermar 297
	/* skip r12 (stack pointer) */
470 jermar 298
	mov loc28 = r13
299
	mov loc29 = r14
300
	mov loc30 = r15
301
	mov loc31 = r16
302
	mov loc32 = r17
303
	mov loc33 = r18
304
	mov loc34 = r19
305
	mov loc35 = r20
306
	mov loc36 = r21
307
	mov loc37 = r22
308
	mov loc38 = r23
309
	mov loc39 = r24
310
	mov loc40 = r25
311
	mov loc41 = r26
312
	mov loc42 = r27
313
	mov loc43 = r28
314
	mov loc44 = r29
315
	mov loc45 = r30
316
	mov loc46 = r31
979 vana 317
 
318
	/*preserve Floating point status register*/
319
	mov loc47 = ar.fpsr
438 jermar 320
 
435 jermar 321
    /* 9. skipped (will not enable interrupts) */
478 jermar 322
	/*
323
    	 * ssm PSR_I_MASK
324
	 * ;;
325
	 * srlz.d
326
	 */
238 vana 327
 
438 jermar 328
    /* 10. call handler */
919 jermar 329
    	movl r1 = _hardcoded_load_address
330
 
470 jermar 331
    	mov b1 = loc2
438 jermar 332
	br.call.sptk.many b0 = b1
333
 
334
    /* 11. return from handler */
335
0:
336
 
435 jermar 337
    /* 12. skipped (will not disable interrupts) */
478 jermar 338
	/*
339
    	 * rsm PSR_I_MASK
340
	 * ;;
341
	 * srlz.d
342
	 */
438 jermar 343
 
435 jermar 344
    /* 13. restore general and floating-point registers */
345
	/* TODO: restore floating-point context */
470 jermar 346
	mov r1 = loc17
347
	mov r2 = loc18
348
	mov r3 = loc19
349
	mov r4 = loc20
350
	mov r5 = loc21
351
	mov r6 = loc22
352
	mov r7 = loc23
921 jermar 353
(p5)	mov r8 = loc24		/* only if not in break_instruction handler */
470 jermar 354
	mov r9 = loc25
355
	mov r10 = loc26
356
	mov r11 = loc27
438 jermar 357
	/* skip r12 (stack pointer) */
470 jermar 358
	mov r13 = loc28
359
	mov r14 = loc29
360
	mov r15 = loc30
361
	mov r16 = loc31
362
	mov r17 = loc32
363
	mov r18 = loc33
364
	mov r19 = loc34
365
	mov r20 = loc35
366
	mov r21 = loc36
367
	mov r22 = loc37
368
	mov r23 = loc38
369
	mov r24 = loc39
370
	mov r25 = loc40
371
	mov r26 = loc41 
372
	mov r27 = loc42
373
	mov r28 = loc43
374
	mov r29 = loc44
375
	mov r30 = loc45
376
	mov r31 = loc46
435 jermar 377
 
979 vana 378
 
379
	/*restore Floating point status register*/
380
	mov ar.fpsr = loc47
381
 
435 jermar 382
    /* 14. restore branch and application registers */
470 jermar 383
    	mov ar.unat = loc3
384
	mov ar.lc = loc4
385
	mov ar.ec = loc5
386
	mov ar.ccv = loc6
387
	mov ar.csd = loc7
388
	mov ar.ssd = loc8
435 jermar 389
 
470 jermar 390
	mov b0 = loc9
391
	mov b1 = loc10
392
	mov b2 = loc11
393
	mov b3 = loc12
394
	mov b4 = loc13
395
	mov b5 = loc14
396
	mov b6 = loc15
397
	mov b7 = loc16
438 jermar 398
 
435 jermar 399
    /* 15. disable PSR.ic and switch to bank 0 */
478 jermar 400
	rsm PSR_IC_MASK
435 jermar 401
	bsw.0 ;;
402
	srlz.d
438 jermar 403
 
911 jermar 404
	mov R_RET = loc1
438 jermar 405
	mov ar.pfs = loc0
470 jermar 406
	br.ret.sptk.many b0
438 jermar 407
 
470 jermar 408
.global ivt
409
.align 32768
410
ivt:
411
	HEAVYWEIGHT_HANDLER 0x0000
412
	HEAVYWEIGHT_HANDLER 0x0400
413
	HEAVYWEIGHT_HANDLER 0x0800
899 jermar 414
	HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault
415
	HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault
416
	HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault
470 jermar 417
	HEAVYWEIGHT_HANDLER 0x1800
418
	HEAVYWEIGHT_HANDLER 0x1c00
899 jermar 419
	HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault
420
	HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault
421
	HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault
470 jermar 422
	HEAVYWEIGHT_HANDLER 0x2c00 break_instruction
423
	HEAVYWEIGHT_HANDLER 0x3000 external_interrupt	/* For external interrupt, heavyweight handler is used. */
424
	HEAVYWEIGHT_HANDLER 0x3400
425
	HEAVYWEIGHT_HANDLER 0x3800
426
	HEAVYWEIGHT_HANDLER 0x3c00
427
	HEAVYWEIGHT_HANDLER 0x4000
428
	HEAVYWEIGHT_HANDLER 0x4400
429
	HEAVYWEIGHT_HANDLER 0x4800
430
	HEAVYWEIGHT_HANDLER 0x4c00
444 vana 431
 
899 jermar 432
	HEAVYWEIGHT_HANDLER 0x5000 page_not_present
470 jermar 433
	HEAVYWEIGHT_HANDLER 0x5100
434
	HEAVYWEIGHT_HANDLER 0x5200
435
	HEAVYWEIGHT_HANDLER 0x5300
436
	HEAVYWEIGHT_HANDLER 0x5400 general_exception
437
	HEAVYWEIGHT_HANDLER 0x5500
438
	HEAVYWEIGHT_HANDLER 0x5600
439
	HEAVYWEIGHT_HANDLER 0x5700
440
	HEAVYWEIGHT_HANDLER 0x5800
441
	HEAVYWEIGHT_HANDLER 0x5900
442
	HEAVYWEIGHT_HANDLER 0x5a00
443
	HEAVYWEIGHT_HANDLER 0x5b00
444
	HEAVYWEIGHT_HANDLER 0x5c00
445
	HEAVYWEIGHT_HANDLER 0x5d00
446
	HEAVYWEIGHT_HANDLER 0x5e00
447
	HEAVYWEIGHT_HANDLER 0x5f00
435 jermar 448
 
470 jermar 449
	HEAVYWEIGHT_HANDLER 0x6000
450
	HEAVYWEIGHT_HANDLER 0x6100
451
	HEAVYWEIGHT_HANDLER 0x6200
452
	HEAVYWEIGHT_HANDLER 0x6300
453
	HEAVYWEIGHT_HANDLER 0x6400
454
	HEAVYWEIGHT_HANDLER 0x6500
455
	HEAVYWEIGHT_HANDLER 0x6600
456
	HEAVYWEIGHT_HANDLER 0x6700
457
	HEAVYWEIGHT_HANDLER 0x6800
458
	HEAVYWEIGHT_HANDLER 0x6900
459
	HEAVYWEIGHT_HANDLER 0x6a00
460
	HEAVYWEIGHT_HANDLER 0x6b00
461
	HEAVYWEIGHT_HANDLER 0x6c00
462
	HEAVYWEIGHT_HANDLER 0x6d00
463
	HEAVYWEIGHT_HANDLER 0x6e00
464
	HEAVYWEIGHT_HANDLER 0x6f00
435 jermar 465
 
470 jermar 466
	HEAVYWEIGHT_HANDLER 0x7000
467
	HEAVYWEIGHT_HANDLER 0x7100
468
	HEAVYWEIGHT_HANDLER 0x7200
469
	HEAVYWEIGHT_HANDLER 0x7300
470
	HEAVYWEIGHT_HANDLER 0x7400
471
	HEAVYWEIGHT_HANDLER 0x7500
472
	HEAVYWEIGHT_HANDLER 0x7600
473
	HEAVYWEIGHT_HANDLER 0x7700
474
	HEAVYWEIGHT_HANDLER 0x7800
475
	HEAVYWEIGHT_HANDLER 0x7900
476
	HEAVYWEIGHT_HANDLER 0x7a00
477
	HEAVYWEIGHT_HANDLER 0x7b00
478
	HEAVYWEIGHT_HANDLER 0x7c00
479
	HEAVYWEIGHT_HANDLER 0x7d00
480
	HEAVYWEIGHT_HANDLER 0x7e00
481
	HEAVYWEIGHT_HANDLER 0x7f00