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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 212 | vana | 1 | # |
| 2 | # Copyright (C) 2005 Jakub Vana |
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| 3 | # All rights reserved. |
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| 4 | # |
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| 5 | # Redistribution and use in source and binary forms, with or without |
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| 6 | # modification, are permitted provided that the following conditions |
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| 7 | # are met: |
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| 8 | # |
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| 9 | # - Redistributions of source code must retain the above copyright |
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| 10 | # notice, this list of conditions and the following disclaimer. |
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| 11 | # - Redistributions in binary form must reproduce the above copyright |
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| 12 | # notice, this list of conditions and the following disclaimer in the |
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| 13 | # documentation and/or other materials provided with the distribution. |
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| 14 | # - The name of the author may not be used to endorse or promote products |
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| 15 | # derived from this software without specific prior written permission. |
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| 16 | # |
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| 17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | # |
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| 28 | |||
| 29 | |||
| 435 | jermar | 30 | /* |
| 31 | * This macro roughly follows steps from 1 to 19 described in |
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| 32 | * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2. |
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| 33 | * |
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| 34 | * Some steps are skipped (enabling and disabling interrupts). |
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| 35 | * Some steps are not fully supported yet (e.g. interruptions |
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| 36 | * from user space and floating-point context). |
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| 37 | */ |
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| 38 | .macro HEAVYWEIGHT_HANDLER offs handler |
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| 39 | .org IVT + \offs |
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| 40 | SAVE_INTERRUPTED_CONTEXT /* steps 1 - 9 */ |
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| 41 | br.call.sptk.many rp = \handler /* steps 10 - 11 */ |
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| 42 | br restore_interrupted_context /* steps 12 - 19 */ |
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| 43 | .endm |
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| 212 | vana | 44 | |
| 435 | jermar | 45 | .macro SAVE_INTERRUPTED_CONTEXT |
| 46 | /* 1. copy interrupt registers into bank 0 */ |
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| 47 | mov r24 = cr.iip |
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| 48 | mov r25 = cr.ipsr |
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| 49 | mov r26 = cr.iipa |
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| 50 | mov r27 = cr.isr |
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| 51 | mov r28 = cr.ifa |
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| 52 | |||
| 53 | /* 2. preserve predicate register into bank 0 */ |
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| 54 | mov r29 = pr ;; |
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| 55 | |||
| 56 | /* 3. switch to kernel memory stack */ |
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| 57 | /* TODO: support interruptions from userspace */ |
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| 58 | /* assume kernel stack */ |
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| 59 | |||
| 60 | /* 4. allocate memory stack for registers saved in bank 0 */ |
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| 61 | st8 [r12] = r29, -8 ;; /* save predicate registers */ |
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| 62 | st8 [r12] = r28, -8 ;; /* save cr.ifa */ |
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| 63 | st8 [r12] = r27, -8 ;; /* save cr.isr */ |
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| 64 | st8 [r12] = r26, -8 ;; /* save cr.iipa */ |
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| 65 | st8 [r12] = r25, -8 ;; /* save cr.ipsr */ |
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| 66 | st8 [r12] = r24, -8 ;; /* save cr.iip */ |
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| 67 | |||
| 68 | /* 5. RSE switch */ |
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| 69 | .auto |
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| 70 | mov r24 = ar.rsc |
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| 71 | mov r25 = ar.pfs |
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| 72 | cover |
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| 73 | mov r26 = cr.ifs |
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| 74 | |||
| 75 | st8 [r12] = r24, -8 /* save ar.rsc */ |
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| 76 | st8 [r12] = r25, -8 /* save ar.pfs */ |
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| 77 | st8 [r12] = r26, -8 /* save ar.ifs */ |
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| 78 | |||
| 79 | and r30 = ~3, r24 |
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| 80 | mov ar.rsc = r30 /* place RSE in enforced lazy mode */ |
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| 81 | |||
| 82 | mov r27 = ar.rnat |
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| 83 | mov r28 = ar.bspstore |
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| 84 | |||
| 85 | /* assume kernel backing store */ |
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| 86 | mov ar.bspstore = r28 |
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| 87 | |||
| 88 | mov r29 = ar.bsp |
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| 89 | |||
| 90 | st8 [r12] = r27, -8 /* save ar.rnat */ |
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| 91 | st8 [r12] = r28, -8 /* save ar.bspstore */ |
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| 92 | st8 [r12] = r29, -8 /* save ar.bsp */ |
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| 93 | |||
| 94 | mov ar.rsc = r24 /* restore RSE's setting */ |
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| 95 | .explicit |
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| 96 | |||
| 97 | /* 6. switch to bank 1 and reenable PSR.ic */ |
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| 98 | ssm 0x2000 |
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| 99 | bsw.1 ;; |
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| 100 | srlz.d |
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| 101 | |||
| 102 | /* 7. preserve branch and application registers */ |
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| 103 | |||
| 104 | /* 8. preserve general and floating-point registers */ |
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| 105 | /* TODO: save floating-point context */ |
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| 106 | |||
| 107 | /* 9. skipped (will not enable interrupts) */ |
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| 108 | .endm |
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| 238 | vana | 109 | |
| 435 | jermar | 110 | .macro RESTORE_INTERRUPTED_CONTEXT |
| 111 | /* 12. skipped (will not disable interrupts) */ |
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| 112 | |||
| 113 | /* 13. restore general and floating-point registers */ |
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| 114 | /* TODO: restore floating-point context */ |
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| 115 | |||
| 116 | /* 14. restore branch and application registers */ |
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| 117 | |||
| 118 | /* 15. disable PSR.ic and switch to bank 0 */ |
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| 119 | rsm 0x2000 |
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| 120 | bsw.0 ;; |
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| 121 | srlz.d |
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| 122 | |||
| 123 | /* 16. RSE switch */ |
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| 124 | |||
| 125 | /* 17. restore interruption state from memory stack */ |
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| 126 | |||
| 127 | /* 18. restore predicate registers from memory stack */ |
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| 128 | |||
| 129 | /* 19. return from interruption */ |
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| 130 | rfi |
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| 131 | .endm |
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| 132 | |||
| 133 | .global restore_interrupted_context |
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| 134 | restore_interrupted_context: |
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| 135 | RESTORE_INTERRUPTED_CONTEXT |
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| 136 | /* not reached */ |
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| 137 | |||
| 238 | vana | 138 | dump_gregs: |
| 139 | mov r16 = REG_DUMP;; |
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| 140 | st8 [r16] = r0;; |
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| 141 | add r16 = 8,r16 ;; |
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| 142 | st8 [r16] = r1;; |
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| 143 | add r16 = 8,r16 ;; |
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| 144 | st8 [r16] = r2;; |
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| 145 | add r16 = 8,r16 ;; |
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| 146 | st8 [r16] = r3;; |
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| 147 | add r16 = 8,r16 ;; |
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| 148 | st8 [r16] = r4;; |
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| 149 | add r16 = 8,r16 ;; |
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| 150 | st8 [r16] = r5;; |
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| 151 | add r16 = 8,r16 ;; |
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| 152 | st8 [r16] = r6;; |
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| 153 | add r16 = 8,r16 ;; |
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| 154 | st8 [r16] = r7;; |
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| 155 | add r16 = 8,r16 ;; |
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| 156 | st8 [r16] = r8;; |
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| 157 | add r16 = 8,r16 ;; |
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| 158 | st8 [r16] = r9;; |
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| 159 | add r16 = 8,r16 ;; |
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| 160 | st8 [r16] = r10;; |
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| 161 | add r16 = 8,r16 ;; |
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| 162 | st8 [r16] = r11;; |
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| 163 | add r16 = 8,r16 ;; |
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| 164 | st8 [r16] = r12;; |
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| 165 | add r16 = 8,r16 ;; |
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| 166 | st8 [r16] = r13;; |
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| 167 | add r16 = 8,r16 ;; |
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| 168 | st8 [r16] = r14;; |
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| 169 | add r16 = 8,r16 ;; |
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| 170 | st8 [r16] = r15;; |
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| 171 | add r16 = 8,r16 ;; |
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| 172 | |||
| 173 | bsw.1;; |
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| 174 | mov r15 = r16;; |
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| 175 | bsw.0;; |
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| 176 | st8 [r16] = r15;; |
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| 177 | add r16 = 8,r16 ;; |
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| 178 | bsw.1;; |
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| 179 | mov r15 = r17;; |
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| 180 | bsw.0;; |
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| 181 | st8 [r16] = r15;; |
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| 182 | add r16 = 8,r16 ;; |
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| 183 | bsw.1;; |
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| 184 | mov r15 = r18;; |
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| 185 | bsw.0;; |
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| 186 | st8 [r16] = r15;; |
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| 187 | add r16 = 8,r16 ;; |
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| 188 | bsw.1;; |
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| 189 | mov r15 = r19;; |
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| 190 | bsw.0;; |
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| 191 | st8 [r16] = r15;; |
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| 192 | add r16 = 8,r16 ;; |
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| 193 | bsw.1;; |
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| 194 | mov r15 = r20;; |
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| 195 | bsw.0;; |
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| 196 | st8 [r16] = r15;; |
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| 197 | add r16 = 8,r16 ;; |
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| 198 | bsw.1;; |
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| 199 | mov r15 = r21;; |
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| 200 | bsw.0;; |
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| 201 | st8 [r16] = r15;; |
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| 202 | add r16 = 8,r16 ;; |
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| 203 | bsw.1;; |
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| 204 | mov r15 = r22;; |
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| 205 | bsw.0;; |
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| 206 | st8 [r16] = r15;; |
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| 207 | add r16 = 8,r16 ;; |
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| 208 | bsw.1;; |
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| 209 | mov r15 = r23;; |
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| 210 | bsw.0;; |
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| 211 | st8 [r16] = r15;; |
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| 212 | add r16 = 8,r16 ;; |
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| 213 | bsw.1;; |
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| 214 | mov r15 = r24;; |
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| 215 | bsw.0;; |
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| 216 | st8 [r16] = r15;; |
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| 217 | add r16 = 8,r16 ;; |
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| 218 | bsw.1;; |
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| 219 | mov r15 = r25;; |
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| 220 | bsw.0;; |
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| 221 | st8 [r16] = r15;; |
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| 222 | add r16 = 8,r16 ;; |
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| 223 | bsw.1;; |
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| 224 | mov r15 = r26;; |
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| 225 | bsw.0;; |
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| 226 | st8 [r16] = r15;; |
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| 227 | add r16 = 8,r16 ;; |
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| 228 | bsw.1;; |
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| 229 | mov r15 = r27;; |
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| 230 | bsw.0;; |
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| 231 | st8 [r16] = r15;; |
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| 232 | add r16 = 8,r16 ;; |
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| 233 | bsw.1;; |
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| 234 | mov r15 = r28;; |
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| 235 | bsw.0;; |
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| 236 | st8 [r16] = r15;; |
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| 237 | add r16 = 8,r16 ;; |
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| 238 | bsw.1;; |
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| 239 | mov r15 = r29;; |
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| 240 | bsw.0;; |
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| 241 | st8 [r16] = r15;; |
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| 242 | add r16 = 8,r16 ;; |
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| 243 | bsw.1;; |
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| 244 | mov r15 = r30;; |
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| 245 | bsw.0;; |
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| 246 | st8 [r16] = r15;; |
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| 247 | add r16 = 8,r16 ;; |
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| 248 | bsw.1;; |
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| 249 | mov r15 = r31;; |
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| 250 | bsw.0;; |
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| 251 | st8 [r16] = r15;; |
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| 252 | add r16 = 8,r16 ;; |
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| 253 | |||
| 254 | |||
| 255 | st8 [r16] = r32;; |
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| 256 | add r16 = 8,r16 ;; |
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| 257 | st8 [r16] = r33;; |
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| 258 | add r16 = 8,r16 ;; |
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| 259 | st8 [r16] = r34;; |
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| 260 | add r16 = 8,r16 ;; |
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| 261 | st8 [r16] = r35;; |
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| 262 | add r16 = 8,r16 ;; |
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| 263 | st8 [r16] = r36;; |
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| 264 | add r16 = 8,r16 ;; |
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| 265 | st8 [r16] = r37;; |
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| 266 | add r16 = 8,r16 ;; |
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| 267 | st8 [r16] = r38;; |
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| 268 | add r16 = 8,r16 ;; |
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| 269 | st8 [r16] = r39;; |
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| 270 | add r16 = 8,r16 ;; |
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| 271 | st8 [r16] = r40;; |
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| 272 | add r16 = 8,r16 ;; |
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| 273 | st8 [r16] = r41;; |
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| 274 | add r16 = 8,r16 ;; |
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| 275 | st8 [r16] = r42;; |
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| 276 | add r16 = 8,r16 ;; |
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| 277 | st8 [r16] = r43;; |
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| 278 | add r16 = 8,r16 ;; |
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| 279 | st8 [r16] = r44;; |
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| 280 | add r16 = 8,r16 ;; |
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| 281 | st8 [r16] = r45;; |
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| 282 | add r16 = 8,r16 ;; |
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| 283 | st8 [r16] = r46;; |
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| 284 | add r16 = 8,r16 ;; |
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| 285 | st8 [r16] = r47;; |
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| 286 | add r16 = 8,r16 ;; |
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| 287 | st8 [r16] = r48;; |
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| 288 | add r16 = 8,r16 ;; |
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| 289 | st8 [r16] = r49;; |
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| 290 | add r16 = 8,r16 ;; |
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| 291 | st8 [r16] = r50;; |
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| 292 | add r16 = 8,r16 ;; |
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| 293 | st8 [r16] = r51;; |
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| 294 | add r16 = 8,r16 ;; |
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| 295 | st8 [r16] = r52;; |
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| 296 | add r16 = 8,r16 ;; |
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| 297 | st8 [r16] = r53;; |
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| 298 | add r16 = 8,r16 ;; |
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| 299 | st8 [r16] = r54;; |
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| 300 | add r16 = 8,r16 ;; |
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| 301 | st8 [r16] = r55;; |
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| 302 | add r16 = 8,r16 ;; |
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| 303 | st8 [r16] = r56;; |
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| 304 | add r16 = 8,r16 ;; |
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| 305 | st8 [r16] = r57;; |
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| 306 | add r16 = 8,r16 ;; |
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| 307 | st8 [r16] = r58;; |
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| 308 | add r16 = 8,r16 ;; |
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| 309 | st8 [r16] = r59;; |
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| 310 | add r16 = 8,r16 ;; |
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| 311 | st8 [r16] = r60;; |
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| 312 | add r16 = 8,r16 ;; |
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| 313 | st8 [r16] = r61;; |
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| 314 | add r16 = 8,r16 ;; |
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| 315 | st8 [r16] = r62;; |
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| 316 | add r16 = 8,r16 ;; |
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| 317 | st8 [r16] = r63;; |
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| 318 | add r16 = 8,r16 ;; |
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| 319 | |||
| 320 | |||
| 321 | |||
| 322 | st8 [r16] = r64;; |
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| 323 | add r16 = 8,r16 ;; |
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| 324 | st8 [r16] = r65;; |
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| 325 | add r16 = 8,r16 ;; |
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| 326 | st8 [r16] = r66;; |
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| 327 | add r16 = 8,r16 ;; |
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| 328 | st8 [r16] = r67;; |
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| 329 | add r16 = 8,r16 ;; |
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| 330 | st8 [r16] = r68;; |
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| 331 | add r16 = 8,r16 ;; |
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| 332 | st8 [r16] = r69;; |
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| 333 | add r16 = 8,r16 ;; |
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| 334 | st8 [r16] = r70;; |
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| 335 | add r16 = 8,r16 ;; |
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| 336 | st8 [r16] = r71;; |
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| 337 | add r16 = 8,r16 ;; |
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| 338 | st8 [r16] = r72;; |
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| 339 | add r16 = 8,r16 ;; |
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| 340 | st8 [r16] = r73;; |
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| 341 | add r16 = 8,r16 ;; |
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| 342 | st8 [r16] = r74;; |
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| 343 | add r16 = 8,r16 ;; |
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| 344 | st8 [r16] = r75;; |
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| 345 | add r16 = 8,r16 ;; |
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| 346 | st8 [r16] = r76;; |
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| 347 | add r16 = 8,r16 ;; |
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| 348 | st8 [r16] = r77;; |
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| 349 | add r16 = 8,r16 ;; |
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| 350 | st8 [r16] = r78;; |
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| 351 | add r16 = 8,r16 ;; |
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| 352 | st8 [r16] = r79;; |
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| 353 | add r16 = 8,r16 ;; |
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| 354 | st8 [r16] = r80;; |
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| 355 | add r16 = 8,r16 ;; |
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| 356 | st8 [r16] = r81;; |
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| 357 | add r16 = 8,r16 ;; |
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| 358 | st8 [r16] = r82;; |
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| 359 | add r16 = 8,r16 ;; |
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| 360 | st8 [r16] = r83;; |
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| 361 | add r16 = 8,r16 ;; |
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| 362 | st8 [r16] = r84;; |
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| 363 | add r16 = 8,r16 ;; |
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| 364 | st8 [r16] = r85;; |
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| 365 | add r16 = 8,r16 ;; |
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| 366 | st8 [r16] = r86;; |
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| 367 | add r16 = 8,r16 ;; |
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| 368 | st8 [r16] = r87;; |
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| 369 | add r16 = 8,r16 ;; |
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| 370 | st8 [r16] = r88;; |
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| 371 | add r16 = 8,r16 ;; |
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| 372 | st8 [r16] = r89;; |
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| 373 | add r16 = 8,r16 ;; |
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| 374 | st8 [r16] = r90;; |
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| 375 | add r16 = 8,r16 ;; |
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| 376 | st8 [r16] = r91;; |
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| 377 | add r16 = 8,r16 ;; |
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| 378 | st8 [r16] = r92;; |
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| 379 | add r16 = 8,r16 ;; |
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| 380 | st8 [r16] = r93;; |
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| 381 | add r16 = 8,r16 ;; |
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| 382 | st8 [r16] = r94;; |
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| 383 | add r16 = 8,r16 ;; |
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| 384 | st8 [r16] = r95;; |
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| 385 | add r16 = 8,r16 ;; |
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| 386 | |||
| 387 | |||
| 388 | |||
| 389 | st8 [r16] = r96;; |
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| 390 | add r16 = 8,r16 ;; |
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| 391 | st8 [r16] = r97;; |
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| 392 | add r16 = 8,r16 ;; |
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| 393 | st8 [r16] = r98;; |
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| 394 | add r16 = 8,r16 ;; |
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| 395 | st8 [r16] = r99;; |
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| 396 | add r16 = 8,r16 ;; |
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| 397 | st8 [r16] = r100;; |
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| 398 | add r16 = 8,r16 ;; |
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| 399 | st8 [r16] = r101;; |
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| 400 | add r16 = 8,r16 ;; |
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| 401 | st8 [r16] = r102;; |
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| 402 | add r16 = 8,r16 ;; |
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| 403 | st8 [r16] = r103;; |
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| 404 | add r16 = 8,r16 ;; |
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| 405 | st8 [r16] = r104;; |
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| 406 | add r16 = 8,r16 ;; |
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| 407 | st8 [r16] = r105;; |
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| 408 | add r16 = 8,r16 ;; |
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| 409 | st8 [r16] = r106;; |
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| 410 | add r16 = 8,r16 ;; |
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| 411 | st8 [r16] = r107;; |
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| 412 | add r16 = 8,r16 ;; |
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| 413 | st8 [r16] = r108;; |
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| 414 | add r16 = 8,r16 ;; |
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| 415 | st8 [r16] = r109;; |
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| 416 | add r16 = 8,r16 ;; |
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| 417 | st8 [r16] = r110;; |
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| 418 | add r16 = 8,r16 ;; |
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| 419 | st8 [r16] = r111;; |
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| 420 | add r16 = 8,r16 ;; |
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| 421 | st8 [r16] = r112;; |
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| 422 | add r16 = 8,r16 ;; |
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| 423 | st8 [r16] = r113;; |
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| 424 | add r16 = 8,r16 ;; |
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| 425 | st8 [r16] = r114;; |
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| 426 | add r16 = 8,r16 ;; |
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| 427 | st8 [r16] = r115;; |
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| 428 | add r16 = 8,r16 ;; |
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| 429 | st8 [r16] = r116;; |
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| 430 | add r16 = 8,r16 ;; |
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| 431 | st8 [r16] = r117;; |
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| 432 | add r16 = 8,r16 ;; |
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| 433 | st8 [r16] = r118;; |
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| 434 | add r16 = 8,r16 ;; |
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| 435 | st8 [r16] = r119;; |
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| 436 | add r16 = 8,r16 ;; |
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| 437 | st8 [r16] = r120;; |
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| 438 | add r16 = 8,r16 ;; |
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| 439 | st8 [r16] = r121;; |
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| 440 | add r16 = 8,r16 ;; |
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| 441 | st8 [r16] = r122;; |
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| 442 | add r16 = 8,r16 ;; |
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| 443 | st8 [r16] = r123;; |
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| 444 | add r16 = 8,r16 ;; |
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| 445 | st8 [r16] = r124;; |
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| 446 | add r16 = 8,r16 ;; |
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| 447 | st8 [r16] = r125;; |
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| 448 | add r16 = 8,r16 ;; |
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| 449 | st8 [r16] = r126;; |
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| 450 | add r16 = 8,r16 ;; |
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| 451 | st8 [r16] = r127;; |
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| 452 | add r16 = 8,r16 ;; |
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| 453 | |||
| 454 | |||
| 455 | |||
| 456 | br.ret.sptk.many b0;; |
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| 457 | |||
| 458 | |||
| 459 | |||
| 460 | |||
| 461 | |||
| 212 | vana | 462 | .macro Handler o h |
| 463 | .org IVT + \o |
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| 464 | br \h;; |
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| 465 | .endm |
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| 466 | |||
| 220 | vana | 467 | .macro Handler2 o |
| 468 | .org IVT + \o |
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| 238 | vana | 469 | br.call.sptk.many b0 = dump_gregs;; |
| 470 | mov r16 = \o ;; |
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| 471 | bsw.1;; |
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| 220 | vana | 472 | br universal_handler;; |
| 473 | .endm |
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| 212 | vana | 474 | |
| 475 | |||
| 220 | vana | 476 | |
| 212 | vana | 477 | .global IVT |
| 478 | .align 32768 |
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| 479 | IVT: |
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| 480 | |||
| 220 | vana | 481 | |
| 482 | Handler2 0x0000 |
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| 483 | Handler2 0x0400 |
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| 484 | Handler2 0x0800 |
||
| 485 | Handler2 0x0c00 |
||
| 486 | Handler2 0x1000 |
||
| 487 | Handler2 0x1400 |
||
| 488 | Handler2 0x1800 |
||
| 489 | Handler2 0x1c00 |
||
| 490 | Handler2 0x2000 |
||
| 491 | Handler2 0x2400 |
||
| 492 | Handler2 0x2800 |
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| 212 | vana | 493 | Handler 0x2c00 break_instruction |
| 435 | jermar | 494 | HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */ |
| 220 | vana | 495 | Handler2 0x3400 |
| 496 | Handler2 0x3800 |
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| 497 | Handler2 0x3c00 |
||
| 498 | Handler2 0x4000 |
||
| 499 | Handler2 0x4400 |
||
| 500 | Handler2 0x4800 |
||
| 501 | Handler2 0x4c00 |
||
| 502 | |||
| 503 | Handler2 0x5000 |
||
| 504 | Handler2 0x5100 |
||
| 505 | Handler2 0x5200 |
||
| 506 | Handler2 0x5300 |
||
| 238 | vana | 507 | #Handler 0x5400 general_exception |
| 508 | Handler2 0x5400 |
||
| 220 | vana | 509 | Handler2 0x5500 |
| 510 | Handler2 0x5600 |
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| 511 | Handler2 0x5700 |
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| 512 | Handler2 0x5800 |
||
| 513 | Handler2 0x5900 |
||
| 514 | Handler2 0x5a00 |
||
| 515 | Handler2 0x5b00 |
||
| 516 | Handler2 0x5c00 |
||
| 517 | Handler2 0x5d00 |
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| 518 | Handler2 0x5e00 |
||
| 519 | Handler2 0x5f00 |
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| 212 | vana | 520 | |
| 220 | vana | 521 | Handler2 0x6000 |
| 522 | Handler2 0x6100 |
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| 523 | Handler2 0x6200 |
||
| 524 | Handler2 0x6300 |
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| 525 | Handler2 0x6400 |
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| 526 | Handler2 0x6500 |
||
| 527 | Handler2 0x6600 |
||
| 528 | Handler2 0x6700 |
||
| 529 | Handler2 0x6800 |
||
| 530 | Handler2 0x6900 |
||
| 531 | Handler2 0x6a00 |
||
| 532 | Handler2 0x6b00 |
||
| 533 | Handler2 0x6c00 |
||
| 534 | Handler2 0x6d00 |
||
| 535 | Handler2 0x6e00 |
||
| 536 | Handler2 0x6f00 |
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| 212 | vana | 537 | |
| 220 | vana | 538 | Handler2 0x7000 |
| 539 | Handler2 0x7100 |
||
| 540 | Handler2 0x7200 |
||
| 541 | Handler2 0x7300 |
||
| 542 | Handler2 0x7400 |
||
| 543 | Handler2 0x7500 |
||
| 544 | Handler2 0x7600 |
||
| 545 | Handler2 0x7700 |
||
| 546 | Handler2 0x7800 |
||
| 547 | Handler2 0x7900 |
||
| 548 | Handler2 0x7a00 |
||
| 549 | Handler2 0x7b00 |
||
| 550 | Handler2 0x7c00 |
||
| 551 | Handler2 0x7d00 |
||
| 552 | Handler2 0x7e00 |
||
| 553 | Handler2 0x7f00 |
||
| 212 | vana | 554 | |
| 555 | |||
| 220 | vana | 556 | |
| 557 | |||
| 558 | |||
| 559 | |||
| 560 | |||
| 561 | |||
| 212 | vana | 562 | .align 32768 |
| 238 | vana | 563 | .global REG_DUMP |
| 564 | |||
| 565 | REG_DUMP: |
||
| 566 | .space 128*8 |
||
| 567 |