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432 jermar 1
/*
2071 jermar 2
 * Copyright (c) 2005 Jakub Jermar
432 jermar 3
 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup ia64   
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 * @{
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 */
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/** @file
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 */
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#ifndef KERN_ia64_REGISTER_H_
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#define KERN_ia64_REGISTER_H_
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#define CR_IVR_MASK 0xf
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#define PSR_IC_MASK 0x2000
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#define PSR_I_MASK  0x4000
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#define PSR_PK_MASK 0x8000
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4153 mejdrech 43
#define PSR_DT_MASK (1 << 17)
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#define PSR_RT_MASK (1 << 27)
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#define PSR_DFL_MASK    (1 << 18)
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#define PSR_DFH_MASK    (1 << 19)
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#define PSR_IT_MASK 0x0000001000000000
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#define PSR_CPL_SHIFT       32
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#define PSR_CPL_MASK_SHIFTED    3
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#define PFM_MASK        (~0x3fffffffff)
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#define RSC_MODE_MASK   3
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#define RSC_PL_MASK 12
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/** Application registers. */
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#define AR_KR0      0
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#define AR_KR1      1
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#define AR_KR2      2
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#define AR_KR3      3
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#define AR_KR4      4
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#define AR_KR5      5
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#define AR_KR6      6
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#define AR_KR7      7
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/* AR 8-15 reserved */
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#define AR_RSC      16
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#define AR_BSP      17
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#define AR_BSPSTORE 18
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#define AR_RNAT     19
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/* AR 20 reserved */
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#define AR_FCR      21
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/* AR 22-23 reserved */
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#define AR_EFLAG    24
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#define AR_CSD      25
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#define AR_SSD      26
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#define AR_CFLG     27
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#define AR_FSR      28
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#define AR_FIR      29
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#define AR_FDR      30
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/* AR 31 reserved */
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#define AR_CCV      32
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/* AR 33-35 reserved */
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#define AR_UNAT     36
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/* AR 37-39 reserved */
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#define AR_FPSR     40
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/* AR 41-43 reserved */
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#define AR_ITC      44
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/* AR 45-47 reserved */
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/* AR 48-63 ignored */
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#define AR_PFS      64
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#define AR_LC       65
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#define AR_EC       66
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/* AR 67-111 reserved */
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/* AR 112-127 ignored */
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/** Control registers. */
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#define CR_DCR      0
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#define CR_ITM      1
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#define CR_IVA      2
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/* CR3-CR7 reserved */
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#define CR_PTA      8
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/* CR9-CR15 reserved */
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#define CR_IPSR     16
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#define CR_ISR      17
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/* CR18 reserved */
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#define CR_IIP      19
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#define CR_IFA      20
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#define CR_ITIR     21
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#define CR_IIPA     22
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#define CR_IFS      23
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#define CR_IIM      24
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#define CR_IHA      25
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/* CR26-CR63 reserved */
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#define CR_LID      64
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#define CR_IVR      65
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#define CR_TPR      66
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#define CR_EOI      67
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#define CR_IRR0     68
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#define CR_IRR1     69
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#define CR_IRR2     70
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#define CR_IRR3     71
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#define CR_ITV      72
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#define CR_PMV      73
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#define CR_CMCV     74
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/* CR75-CR79 reserved */
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#define CR_LRR0     80
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#define CR_LRR1     81
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/* CR82-CR127 reserved */
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#ifndef __ASM__
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#include <arch/types.h>
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/** Processor Status Register. */
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union psr {
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    uint64_t value;
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    struct {
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        unsigned : 1;
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        unsigned be : 1;    /**< Big-Endian data accesses. */
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        unsigned up : 1;    /**< User Performance monitor enable. */
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        unsigned ac : 1;    /**< Alignment Check. */
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        unsigned mfl : 1;   /**< Lower floating-point register written. */
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        unsigned mfh : 1;   /**< Upper floating-point register written. */
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        unsigned : 7;
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        unsigned ic : 1;    /**< Interruption Collection. */
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        unsigned i : 1;     /**< Interrupt Bit. */
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        unsigned pk : 1;    /**< Protection Key enable. */
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        unsigned : 1;
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        unsigned dt : 1;    /**< Data address Translation. */
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        unsigned dfl : 1;   /**< Disabled Floating-point Low register set. */
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        unsigned dfh : 1;   /**< Disabled Floating-point High register set. */
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        unsigned sp : 1;    /**< Secure Performance monitors. */
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        unsigned pp : 1;    /**< Privileged Performance monitor enable. */
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        unsigned di : 1;    /**< Disable Instruction set transition. */
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        unsigned si : 1;    /**< Secure Interval timer. */
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        unsigned db : 1;    /**< Debug Breakpoint fault. */
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        unsigned lp : 1;    /**< Lower Privilege transfer trap. */
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        unsigned tb : 1;    /**< Taken Branch trap. */
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        unsigned rt : 1;    /**< Register Stack Translation. */
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        unsigned : 4;
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        unsigned cpl : 2;   /**< Current Privilege Level. */
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        unsigned is : 1;    /**< Instruction Set. */
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        unsigned mc : 1;    /**< Machine Check abort mask. */
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        unsigned it : 1;    /**< Instruction address Translation. */
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        unsigned id : 1;    /**< Instruction Debug fault disable. */
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        unsigned da : 1;    /**< Disable Data Access and Dirty-bit faults. */
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        unsigned dd : 1;    /**< Data Debug fault disable. */
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        unsigned ss : 1;    /**< Single Step enable. */
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        unsigned ri : 2;    /**< Restart Instruction. */
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        unsigned ed : 1;    /**< Exception Deferral. */
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        unsigned bn : 1;    /**< Register Bank. */
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        unsigned ia : 1;    /**< Disable Instruction Access-bit faults. */
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    } __attribute__ ((packed));
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};
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typedef union psr psr_t;
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/** Register Stack Configuration Register */
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union rsc {
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    uint64_t value;
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    struct {
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        unsigned mode : 2;
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        unsigned pl : 2;    /**< Privilege Level. */
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        unsigned be : 1;    /**< Big-endian. */
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        unsigned : 11;
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        unsigned loadrs : 14;
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    } __attribute__ ((packed));
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};
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typedef union rsc rsc_t;
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/** External Interrupt Vector Register */
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union cr_ivr {
1780 jermar 195
    uint8_t  vector;
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    uint64_t value;
433 jermar 197
};
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typedef union cr_ivr cr_ivr_t;
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/** Task Priority Register */
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union cr_tpr {
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    struct {
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        unsigned : 4;
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        unsigned mic: 4;        /**< Mask Interrupt Class. */
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        unsigned : 8;
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        unsigned mmi: 1;        /**< Mask Maskable Interrupts. */
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    } __attribute__ ((packed));
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    uint64_t value;
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};
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212
typedef union cr_tpr cr_tpr_t;
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/** Interval Timer Vector */
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union cr_itv {
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    struct {
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        unsigned vector : 8;
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        unsigned : 4;
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        unsigned : 1;
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        unsigned : 3;
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        unsigned m : 1;         /**< Mask. */
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    } __attribute__ ((packed));
1780 jermar 223
    uint64_t value;
433 jermar 224
};
225
 
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typedef union cr_itv cr_itv_t;
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472 jermar 228
/** Interruption Status Register */
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union cr_isr {
230
    struct {
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        union {
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            /** General Exception code field structuring. */
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            struct {
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                unsigned ge_na : 4;
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                unsigned ge_code : 4;
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            } __attribute__ ((packed));
1780 jermar 237
            uint16_t code;
472 jermar 238
        };
1780 jermar 239
        uint8_t vector;
472 jermar 240
        unsigned : 8;
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        unsigned x : 1;         /**< Execute exception. */
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        unsigned w : 1;         /**< Write exception. */
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        unsigned r : 1;         /**< Read exception. */
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        unsigned na : 1;        /**< Non-access exception. */
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        unsigned sp : 1;        /**< Speculative load exception. */
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        unsigned rs : 1;        /**< Register stack. */
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        unsigned ir : 1;        /**< Incomplete Register frame. */
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        unsigned ni : 1;        /**< Nested Interruption. */
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        unsigned so : 1;        /**< IA-32 Supervisor Override. */
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        unsigned ei : 2;        /**< Excepting Instruction. */
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        unsigned ed : 1;        /**< Exception Deferral. */
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        unsigned : 20;
253
    } __attribute__ ((packed));
1780 jermar 254
    uint64_t value;
472 jermar 255
};
256
 
257
typedef union cr_isr cr_isr_t;
258
 
476 jermar 259
/** CPUID Register 3 */
260
union cpuid3 {
261
    struct {
1780 jermar 262
        uint8_t number;
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        uint8_t revision;
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        uint8_t model;
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        uint8_t family;
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        uint8_t archrev;
476 jermar 267
    } __attribute__ ((packed));
1780 jermar 268
    uint64_t value;
476 jermar 269
};
270
 
271
typedef union cpuid3 cpuid3_t;
272
 
472 jermar 273
#endif /* !__ASM__ */
274
 
432 jermar 275
#endif
1702 cejka 276
 
1888 jermar 277
/** @}
1702 cejka 278
 */