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389 jermar 1
/*
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 * Copyright (c) 2005 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup ia64mm 
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 * @{
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 */
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/** @file
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 */
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#ifndef KERN_ia64_TLB_H_
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#define KERN_ia64_TLB_H_
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#include <arch/mm/page.h>
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#include <arch/mm/asid.h>
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#include <arch/interrupt.h>
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#include <arch/types.h>
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/** Data and instruction Translation Register indices. */
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#define DTR_KERNEL  0
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#define ITR_KERNEL  0
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#define DTR_KSTACK1 4
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#define DTR_KSTACK2 5
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/** Portion of TLB insertion format data structure. */
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union tlb_entry {
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    uint64_t word[2];
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    struct {
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        /* Word 0 */
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        unsigned p : 1;         /**< Present. */
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        unsigned : 1;
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        unsigned ma : 3;        /**< Memory attribute. */
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        unsigned a : 1;         /**< Accessed. */
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        unsigned d : 1;         /**< Dirty. */
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        unsigned pl : 2;        /**< Privilege level. */
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        unsigned ar : 3;        /**< Access rights. */
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        unsigned long long ppn : 38;    /**< Physical Page Number, a.k.a. PFN. */
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        unsigned : 2;
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        unsigned ed : 1;
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        unsigned ig1 : 11;
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        /* Word 1 */
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        unsigned : 2;
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        unsigned ps : 6;        /**< Page size will be 2^ps. */
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        unsigned key : 24;      /**< Protection key, unused. */
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        unsigned : 32;
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    } __attribute__ ((packed));
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} __attribute__ ((packed));
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typedef union tlb_entry tlb_entry_t;
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extern void tc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtc);
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extern void dtc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry);
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extern void itc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry);
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extern void tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr, size_t tr);
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extern void dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr);
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extern void itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr);
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extern void dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr, size_t tr);
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extern void dtr_purge(uintptr_t page, size_t width);
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extern void dtc_pte_copy(pte_t *t);
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extern void itc_pte_copy(pte_t *t);
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extern void alternate_instruction_tlb_fault(uint64_t vector, istate_t *istate);
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extern void alternate_data_tlb_fault(uint64_t vector, istate_t *istate);
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extern void data_nested_tlb_fault(uint64_t vector, istate_t *istate);
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extern void data_dirty_bit_fault(uint64_t vector, istate_t *istate);
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extern void instruction_access_bit_fault(uint64_t vector, istate_t *istate);
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extern void data_access_bit_fault(uint64_t vector, istate_t *istate);
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extern void page_not_present(uint64_t vector, istate_t *istate);
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#endif
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/** @}
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 */