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2128 jermar 1
/*
2465 jermar 2
 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt
2128 jermar 3
 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
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/** @addtogroup arm32mm
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 * @{
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 */
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/** @file
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 *  @brief Paging related declarations.
2128 jermar 34
 */
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36
#ifndef KERN_arm32_PAGE_H_
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#define KERN_arm32_PAGE_H_
38
 
39
#include <arch/mm/frame.h>
2465 jermar 40
#include <mm/mm.h>
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#include <arch/exception.h>
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43
#define PAGE_WIDTH  FRAME_WIDTH
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#define PAGE_SIZE   FRAME_SIZE
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46
#ifndef __ASM__
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#   define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
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#   define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
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#else
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#   define KA2PA(x) ((x) - 0x80000000)
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#   define PA2KA(x) ((x) + 0x80000000)
52
#endif
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54
#ifdef KERNEL
55
 
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/* Number of entries in each level. */
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#define PTL0_ENTRIES_ARCH   (2 << 12)   /* 4096 */
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#define PTL1_ENTRIES_ARCH   0
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#define PTL2_ENTRIES_ARCH   0
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/* coarse page tables used (256 * 4 = 1KB per page) */
61
#define PTL3_ENTRIES_ARCH   (2 << 8)    /* 256 */
2128 jermar 62
 
2467 jermar 63
/* Page table sizes for each level. */
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#define PTL0_SIZE_ARCH      FOUR_FRAMES
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#define PTL1_SIZE_ARCH      0
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#define PTL2_SIZE_ARCH      0
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#define PTL3_SIZE_ARCH      ONE_FRAME
2128 jermar 68
 
2467 jermar 69
/* Macros calculating indices into page tables for each level. */
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#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 20) & 0xfff)
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#define PTL1_INDEX_ARCH(vaddr)  0
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#define PTL2_INDEX_ARCH(vaddr)  0
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#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x0ff)
2128 jermar 74
 
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/* Get PTE address accessors for each level. */
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#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
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    ((pte_t *) ((((pte_level0_t *)(ptl0))[(i)]).coarse_table_addr << 10))
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#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
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    (ptl1)
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#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
81
    (ptl2)
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#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
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    ((uintptr_t) ((((pte_level1_t *)(ptl3))[(i)]).frame_base_addr << 12))
2128 jermar 84
 
2467 jermar 85
/* Set PTE address accessors for each level. */
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#define SET_PTL0_ADDRESS_ARCH(ptl0) \
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    (set_ptl0_addr((pte_level0_t *) (ptl0)))
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#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
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    (((pte_level0_t *) (ptl0))[(i)].coarse_table_addr = (a) >> 10)
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#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
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#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
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#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
93
    (((pte_level1_t *) (ptl3))[(i)].frame_base_addr = (a) >> 12)
2128 jermar 94
 
2467 jermar 95
/* Get PTE flags accessors for each level. */
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#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
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    get_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i))
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#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
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    PAGE_PRESENT
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#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
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    PAGE_PRESENT
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#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
103
    get_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i))
2128 jermar 104
 
2467 jermar 105
/* Set PTE flags accessors for each level. */
2465 jermar 106
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
107
    set_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i), (x))
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#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
109
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
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#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
111
    set_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i), (x))
2128 jermar 112
 
2467 jermar 113
/* Macros for querying the last-level PTE entries. */
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#define PTE_VALID_ARCH(pte) \
115
    (*((uint32_t *) (pte)) != 0)
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#define PTE_PRESENT_ARCH(pte) \
117
    (((pte_level0_t *) (pte))->descriptor_type != 0)
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#define PTE_GET_FRAME_ARCH(pte) \
119
    (((pte_level1_t *) (pte))->frame_base_addr << FRAME_WIDTH)
120
#define PTE_WRITABLE_ARCH(pte) \
121
    (((pte_level1_t *) (pte))->access_permission_0 == \
122
        PTE_AP_USER_RW_KERNEL_RW)
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#define PTE_EXECUTABLE_ARCH(pte) \
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    1
125
 
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#ifndef __ASM__
127
 
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/** Level 0 page table entry. */
129
typedef struct {
130
    /* 0b01 for coarse tables, see below for details */
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    unsigned descriptor_type : 2;
132
    unsigned impl_specific : 3;
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    unsigned domain : 4;
134
    unsigned should_be_zero : 1;
2128 jermar 135
 
2465 jermar 136
    /* Pointer to the coarse 2nd level page table (holding entries for small
137
     * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page
138
     * tables that may hold even tiny pages (1KB) but they are bigger (4KB
139
     * per table in comparison with 1KB per the coarse table)
140
     */
2467 jermar 141
    unsigned coarse_table_addr : 22;
2465 jermar 142
} ATTRIBUTE_PACKED pte_level0_t;
143
 
144
/** Level 1 page table entry (small (4KB) pages used). */
145
typedef struct {
146
 
147
    /* 0b10 for small pages */
2467 jermar 148
    unsigned descriptor_type : 2;
149
    unsigned bufferable : 1;
150
    unsigned cacheable : 1;
2465 jermar 151
 
152
    /* access permissions for each of 4 subparts of a page
153
     * (for each 1KB when small pages used */
154
    unsigned access_permission_0 : 2;
155
    unsigned access_permission_1 : 2;
156
    unsigned access_permission_2 : 2;
157
    unsigned access_permission_3 : 2;
2467 jermar 158
    unsigned frame_base_addr : 20;
2465 jermar 159
} ATTRIBUTE_PACKED pte_level1_t;
160
 
161
 
162
/* Level 1 page tables access permissions */
163
 
164
/** User mode: no access, privileged mode: no access. */
165
#define PTE_AP_USER_NO_KERNEL_NO    0
166
 
167
/** User mode: no access, privileged mode: read/write. */
168
#define PTE_AP_USER_NO_KERNEL_RW    1
169
 
170
/** User mode: read only, privileged mode: read/write. */
171
#define PTE_AP_USER_RO_KERNEL_RW    2
172
 
173
/** User mode: read/write, privileged mode: read/write. */
174
#define PTE_AP_USER_RW_KERNEL_RW    3
175
 
176
 
177
/* pte_level0_t and pte_level1_t descriptor_type flags */
178
 
179
/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */
180
#define PTE_DESCRIPTOR_NOT_PRESENT  0
181
 
182
/** pte_level0_t coarse page table flag (used in descriptor_type). */
183
#define PTE_DESCRIPTOR_COARSE_TABLE 1
184
 
185
/** pte_level1_t small page table flag (used in descriptor type). */
186
#define PTE_DESCRIPTOR_SMALL_PAGE   2
187
 
188
 
189
/** Sets the address of level 0 page table.
190
 *
191
 * @param pt    Pointer to the page table to set.
192
 */  
2467 jermar 193
static inline void set_ptl0_addr(pte_level0_t *pt)
2128 jermar 194
{
2465 jermar 195
    asm volatile (
4153 mejdrech 196
        "mcr p15, 0, %[pt], c2, c0, 0\n"
197
        :: [pt] "r" (pt)
2465 jermar 198
    );
2128 jermar 199
}
200
 
2465 jermar 201
 
202
/** Returns level 0 page table entry flags.
203
 *
204
 *  @param pt     Level 0 page table.
205
 *  @param i      Index of the entry to return.
206
 */
207
static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i)
2128 jermar 208
{
2465 jermar 209
    pte_level0_t *p = &pt[i];
210
    int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT);
211
 
212
    return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) |
213
        (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) |
214
        (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT);
2128 jermar 215
}
216
 
2465 jermar 217
/** Returns level 1 page table entry flags.
218
 *
219
 *  @param pt     Level 1 page table.
220
 *  @param i      Index of the entry to return.
221
 */
222
static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i)
223
{
224
    pte_level1_t *p = &pt[i];
225
 
226
    int dt = p->descriptor_type;
227
    int ap = p->access_permission_0;
228
 
229
    return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) |
230
        ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) |
231
        ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT) |
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        ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT) |
233
        ((ap != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT) |
234
        ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT) |
235
        ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT) |
236
        (1 << PAGE_EXEC_SHIFT) |
237
        (p->bufferable << PAGE_CACHEABLE);
238
}
239
 
240
 
241
/** Sets flags of level 0 page table entry.
242
 *
243
 *  @param pt     level 0 page table
244
 *  @param i      index of the entry to be changed
245
 *  @param flags  new flags
246
 */
247
static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags)
248
{
249
    pte_level0_t *p = &pt[i];
250
 
251
    if (flags & PAGE_NOT_PRESENT) {
252
        p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
253
        /*
254
         * Ensures that the entry will be recognized as valid when
255
         * PTE_VALID_ARCH applied.
256
         */
257
        p->should_be_zero = 1;
258
    } else {
259
        p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
260
        p->should_be_zero = 0;
261
    }
262
}
263
 
264
 
265
/** Sets flags of level 1 page table entry.
266
 *
267
 *  We use same access rights for the whole page. When page is not preset we
268
 *  store 1 in acess_rigts_3 so that at least one bit is 1 (to mark correct
269
 *  page entry, see #PAGE_VALID_ARCH).
270
 *
271
 *  @param pt     Level 1 page table.
272
 *  @param i      Index of the entry to be changed.
273
 *  @param flags  New flags.
274
 */  
275
static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags)
276
{
277
    pte_level1_t *p = &pt[i];
278
 
279
    if (flags & PAGE_NOT_PRESENT) {
280
        p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
281
        p->access_permission_3 = 1;
282
    } else {
283
        p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
284
        p->access_permission_3 = p->access_permission_0;
285
    }
286
 
287
    p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
288
 
289
    /* default access permission */
290
    p->access_permission_0 = p->access_permission_1 =
291
        p->access_permission_2 = p->access_permission_3 =
292
        PTE_AP_USER_NO_KERNEL_RW;
293
 
294
    if (flags & PAGE_USER)  {
295
        if (flags & PAGE_READ) {
296
            p->access_permission_0 = p->access_permission_1 =
297
                p->access_permission_2 = p->access_permission_3 =
298
                PTE_AP_USER_RO_KERNEL_RW;
299
        }
300
        if (flags & PAGE_WRITE) {
301
            p->access_permission_0 = p->access_permission_1 =
302
                p->access_permission_2 = p->access_permission_3 =
303
                PTE_AP_USER_RW_KERNEL_RW;
304
        }
305
    }
306
}
307
 
308
 
2128 jermar 309
extern void page_arch_init(void);
310
 
2465 jermar 311
 
2128 jermar 312
#endif /* __ASM__ */
313
 
314
#endif /* KERNEL */
315
 
316
#endif
317
 
318
/** @}
319
 */