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173 jermar 1
/*
2071 jermar 2
 * Copyright (c) 2005 Jakub Jermar
173 jermar 3
 * All rights reserved.
4
 *
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
7
 * are met:
8
 *
9
 * - Redistributions of source code must retain the above copyright
10
 *   notice, this list of conditions and the following disclaimer.
11
 * - Redistributions in binary form must reproduce the above copyright
12
 *   notice, this list of conditions and the following disclaimer in the
13
 *   documentation and/or other materials provided with the distribution.
14
 * - The name of the author may not be used to endorse or promote products
15
 *   derived from this software without specific prior written permission.
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
28
 
4153 mejdrech 29
/** @addtogroup amd64
1702 cejka 30
 * @{
31
 */
32
/** @file
33
 */
34
 
1888 jermar 35
#ifndef KERN_amd64_ASM_H_
36
#define KERN_amd64_ASM_H_
173 jermar 37
 
38
#include <config.h>
4153 mejdrech 39
#include <arch/types.h>
40
#include <typedefs.h>
173 jermar 41
 
1780 jermar 42
extern void asm_delay_loop(uint32_t t);
43
extern void asm_fake_loop(uint32_t t);
200 palkovsky 44
 
253 jermar 45
/** Return base address of current stack.
46
 *
47
 * Return the base address of the current stack.
48
 * The stack is assumed to be STACK_SIZE bytes long.
49
 * The stack must start on page boundary.
4153 mejdrech 50
 *
253 jermar 51
 */
1780 jermar 52
static inline uintptr_t get_stack_base(void)
173 jermar 53
{
1780 jermar 54
    uintptr_t v;
226 palkovsky 55
 
4153 mejdrech 56
    asm volatile (
57
        "andq %%rsp, %[v]\n"
58
        : [v] "=r" (v)
59
        : "0" (~((uint64_t) STACK_SIZE-1))
60
    );
226 palkovsky 61
 
62
    return v;
173 jermar 63
}
64
 
2233 decky 65
static inline void cpu_sleep(void)
66
{
67
    asm volatile ("hlt\n");
2453 jermar 68
}
197 palkovsky 69
 
2233 decky 70
static inline void cpu_halt(void)
71
{
4153 mejdrech 72
    asm volatile (
73
        "0:\n"
74
        "   hlt\n"
75
        "   jmp 0b\n"
76
    );
2453 jermar 77
}
200 palkovsky 78
 
2233 decky 79
 
625 palkovsky 80
/** Byte from port
81
 *
82
 * Get byte from port
83
 *
84
 * @param port Port to read from
85
 * @return Value read
4153 mejdrech 86
 *
625 palkovsky 87
 */
4153 mejdrech 88
static inline uint8_t pio_read_8(ioport8_t *port)
2453 jermar 89
{
90
    uint8_t val;
4153 mejdrech 91
 
92
    asm volatile (
93
        "inb %w[port], %b[val]\n"
94
        : [val] "=a" (val)
95
        : [port] "d" (port)
96
    );
97
 
98
    return val;
99
}
200 palkovsky 100
 
4153 mejdrech 101
/** Word from port
102
 *
103
 * Get word from port
104
 *
105
 * @param port Port to read from
106
 * @return Value read
107
 *
108
 */
109
static inline uint16_t pio_read_16(ioport16_t *port)
110
{
111
    uint16_t val;
112
 
113
    asm volatile (
114
        "inw %w[port], %w[val]\n"
115
        : [val] "=a" (val)
116
        : [port] "d" (port)
117
    );
118
 
2453 jermar 119
    return val;
120
}
121
 
4153 mejdrech 122
/** Double word from port
123
 *
124
 * Get double word from port
125
 *
126
 * @param port Port to read from
127
 * @return Value read
128
 *
129
 */
130
static inline uint32_t pio_read_32(ioport32_t *port)
131
{
132
    uint32_t val;
133
 
134
    asm volatile (
135
        "inl %w[port], %[val]\n"
136
        : [val] "=a" (val)
137
        : [port] "d" (port)
138
    );
139
 
140
    return val;
141
}
142
 
625 palkovsky 143
/** Byte to port
144
 *
145
 * Output byte to port
146
 *
147
 * @param port Port to write to
148
 * @param val Value to write
4153 mejdrech 149
 *
625 palkovsky 150
 */
4153 mejdrech 151
static inline void pio_write_8(ioport8_t *port, uint8_t val)
2453 jermar 152
{
4153 mejdrech 153
    asm volatile (
154
        "outb %b[val], %w[port]\n"
155
        :: [val] "a" (val), [port] "d" (port)
156
    );
2453 jermar 157
}
200 palkovsky 158
 
4153 mejdrech 159
/** Word to port
160
 *
161
 * Output word to port
162
 *
163
 * @param port Port to write to
164
 * @param val Value to write
165
 *
166
 */
167
static inline void pio_write_16(ioport16_t *port, uint16_t val)
168
{
169
    asm volatile (
170
        "outw %w[val], %w[port]\n"
171
        :: [val] "a" (val), [port] "d" (port)
172
    );
173
}
174
 
175
/** Double word to port
176
 *
177
 * Output double word to port
178
 *
179
 * @param port Port to write to
180
 * @param val Value to write
181
 *
182
 */
183
static inline void pio_write_32(ioport32_t *port, uint32_t val)
184
{
185
    asm volatile (
186
        "outl %[val], %w[port]\n"
187
        :: [val] "a" (val), [port] "d" (port)
188
    );
189
}
190
 
806 palkovsky 191
/** Swap Hidden part of GS register with visible one */
2453 jermar 192
static inline void swapgs(void)
193
{
194
    asm volatile("swapgs");
195
}
806 palkovsky 196
 
413 jermar 197
/** Enable interrupts.
200 palkovsky 198
 *
199
 * Enable interrupts and return previous
200
 * value of EFLAGS.
413 jermar 201
 *
202
 * @return Old interrupt priority level.
4153 mejdrech 203
 *
200 palkovsky 204
 */
413 jermar 205
static inline ipl_t interrupts_enable(void) {
206
    ipl_t v;
4153 mejdrech 207
 
208
    asm volatile (
200 palkovsky 209
        "pushfq\n"
4153 mejdrech 210
        "popq %[v]\n"
200 palkovsky 211
        "sti\n"
4153 mejdrech 212
        : [v] "=r" (v)
200 palkovsky 213
    );
4153 mejdrech 214
 
200 palkovsky 215
    return v;
216
}
217
 
413 jermar 218
/** Disable interrupts.
200 palkovsky 219
 *
220
 * Disable interrupts and return previous
221
 * value of EFLAGS.
413 jermar 222
 *
223
 * @return Old interrupt priority level.
4153 mejdrech 224
 *
200 palkovsky 225
 */
413 jermar 226
static inline ipl_t interrupts_disable(void) {
227
    ipl_t v;
4153 mejdrech 228
 
229
    asm volatile (
200 palkovsky 230
        "pushfq\n"
4153 mejdrech 231
        "popq %[v]\n"
200 palkovsky 232
        "cli\n"
4153 mejdrech 233
        : [v] "=r" (v)
234
    );
235
 
200 palkovsky 236
    return v;
237
}
238
 
413 jermar 239
/** Restore interrupt priority level.
200 palkovsky 240
 *
241
 * Restore EFLAGS.
413 jermar 242
 *
243
 * @param ipl Saved interrupt priority level.
4153 mejdrech 244
 *
200 palkovsky 245
 */
413 jermar 246
static inline void interrupts_restore(ipl_t ipl) {
4153 mejdrech 247
    asm volatile (
248
        "pushq %[ipl]\n"
200 palkovsky 249
        "popfq\n"
4153 mejdrech 250
        :: [ipl] "r" (ipl)
251
    );
200 palkovsky 252
}
253
 
413 jermar 254
/** Return interrupt priority level.
206 palkovsky 255
 *
256
 * Return EFLAFS.
413 jermar 257
 *
258
 * @return Current interrupt priority level.
4153 mejdrech 259
 *
206 palkovsky 260
 */
413 jermar 261
static inline ipl_t interrupts_read(void) {
262
    ipl_t v;
4153 mejdrech 263
 
264
    asm volatile (
206 palkovsky 265
        "pushfq\n"
4153 mejdrech 266
        "popq %[v]\n"
267
        : [v] "=r" (v)
206 palkovsky 268
    );
4153 mejdrech 269
 
206 palkovsky 270
    return v;
271
}
200 palkovsky 272
 
803 palkovsky 273
/** Write to MSR */
1780 jermar 274
static inline void write_msr(uint32_t msr, uint64_t value)
803 palkovsky 275
{
4153 mejdrech 276
    asm volatile (
277
        "wrmsr\n"
278
        :: "c" (msr),
279
           "a" ((uint32_t) (value)),
280
           "d" ((uint32_t) (value >> 32))
281
    );
803 palkovsky 282
}
219 palkovsky 283
 
1780 jermar 284
static inline unative_t read_msr(uint32_t msr)
803 palkovsky 285
{
1780 jermar 286
    uint32_t ax, dx;
4153 mejdrech 287
 
288
    asm volatile (
289
        "rdmsr\n"
290
        : "=a" (ax), "=d" (dx)
291
        : "c" (msr)
292
    );
293
 
294
    return ((uint64_t) dx << 32) | ax;
803 palkovsky 295
}
296
 
297
 
268 palkovsky 298
/** Enable local APIC
299
 *
300
 * Enable local APIC in MSR.
4153 mejdrech 301
 *
268 palkovsky 302
 */
303
static inline void enable_l_apic_in_msr()
304
{
4153 mejdrech 305
    asm volatile (
348 jermar 306
        "movl $0x1b, %%ecx\n"
307
        "rdmsr\n"
4153 mejdrech 308
        "orl $(1 << 11),%%eax\n"
348 jermar 309
        "orl $(0xfee00000),%%eax\n"
310
        "wrmsr\n"
4153 mejdrech 311
        ::: "%eax","%ecx","%edx"
312
    );
268 palkovsky 313
}
314
 
1780 jermar 315
static inline uintptr_t * get_ip()
581 palkovsky 316
{
1780 jermar 317
    uintptr_t *ip;
4153 mejdrech 318
 
319
    asm volatile (
320
        "mov %%rip, %[ip]"
321
        : [ip] "=r" (ip)
322
    );
323
 
581 palkovsky 324
    return ip;
325
}
326
 
597 jermar 327
/** Invalidate TLB Entry.
328
 *
329
 * @param addr Address on a page whose TLB entry is to be invalidated.
4153 mejdrech 330
 *
597 jermar 331
 */
1780 jermar 332
static inline void invlpg(uintptr_t addr)
597 jermar 333
{
4153 mejdrech 334
    asm volatile (
335
        "invlpg %[addr]\n"
336
        :: [addr] "m" (*((unative_t *) addr))
337
    );
597 jermar 338
}
581 palkovsky 339
 
1186 jermar 340
/** Load GDTR register from memory.
341
 *
342
 * @param gdtr_reg Address of memory from where to load GDTR.
4153 mejdrech 343
 *
1186 jermar 344
 */
4153 mejdrech 345
static inline void gdtr_load(ptr_16_64_t *gdtr_reg)
1186 jermar 346
{
4153 mejdrech 347
    asm volatile (
348
        "lgdtq %[gdtr_reg]\n"
349
        :: [gdtr_reg] "m" (*gdtr_reg)
350
    );
1186 jermar 351
}
352
 
353
/** Store GDTR register to memory.
354
 *
355
 * @param gdtr_reg Address of memory to where to load GDTR.
4153 mejdrech 356
 *
1186 jermar 357
 */
4153 mejdrech 358
static inline void gdtr_store(ptr_16_64_t *gdtr_reg)
1186 jermar 359
{
4153 mejdrech 360
    asm volatile (
361
        "sgdtq %[gdtr_reg]\n"
362
        :: [gdtr_reg] "m" (*gdtr_reg)
363
    );
1186 jermar 364
}
365
 
366
/** Load IDTR register from memory.
367
 *
368
 * @param idtr_reg Address of memory from where to load IDTR.
4153 mejdrech 369
 *
1186 jermar 370
 */
4153 mejdrech 371
static inline void idtr_load(ptr_16_64_t *idtr_reg)
1186 jermar 372
{
4153 mejdrech 373
    asm volatile (
374
        "lidtq %[idtr_reg]\n"
375
        :: [idtr_reg] "m" (*idtr_reg));
1186 jermar 376
}
377
 
378
/** Load TR from descriptor table.
379
 *
380
 * @param sel Selector specifying descriptor of TSS segment.
4153 mejdrech 381
 *
1186 jermar 382
 */
1780 jermar 383
static inline void tr_load(uint16_t sel)
1186 jermar 384
{
4153 mejdrech 385
    asm volatile (
386
        "ltr %[sel]"
387
        :: [sel] "r" (sel)
388
    );
1186 jermar 389
}
390
 
1780 jermar 391
#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
4153 mejdrech 392
    { \
393
        unative_t res; \
394
        asm volatile ( \
395
            "movq %%" #reg ", %[res]" \
396
            : [res] "=r" (res) \
397
        ); \
398
        return res; \
399
    }
1072 palkovsky 400
 
1780 jermar 401
#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
4153 mejdrech 402
    { \
403
        asm volatile ( \
404
            "movq %[regn], %%" #reg \
405
            :: [regn] "r" (regn) \
406
        ); \
407
    }
1072 palkovsky 408
 
2452 jermar 409
GEN_READ_REG(cr0)
410
GEN_READ_REG(cr2)
411
GEN_READ_REG(cr3)
412
GEN_WRITE_REG(cr3)
1072 palkovsky 413
 
2452 jermar 414
GEN_READ_REG(dr0)
415
GEN_READ_REG(dr1)
416
GEN_READ_REG(dr2)
417
GEN_READ_REG(dr3)
418
GEN_READ_REG(dr6)
419
GEN_READ_REG(dr7)
1072 palkovsky 420
 
2452 jermar 421
GEN_WRITE_REG(dr0)
422
GEN_WRITE_REG(dr1)
423
GEN_WRITE_REG(dr2)
424
GEN_WRITE_REG(dr3)
425
GEN_WRITE_REG(dr6)
426
GEN_WRITE_REG(dr7)
1072 palkovsky 427
 
206 palkovsky 428
extern size_t interrupt_handler_size;
429
extern void interrupt_handlers(void);
430
 
173 jermar 431
#endif
1702 cejka 432
 
1888 jermar 433
/** @}
1702 cejka 434
 */