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418 jermar 1
/*
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 * Copyright (C) 2005 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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29
#ifndef __sparc64_TLB_H__
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#define __sparc64_TLB_H__
31
 
530 jermar 32
#include <arch/mm/tte.h>
619 jermar 33
#include <arch/mm/mmu.h>
617 jermar 34
#include <arch/mm/page.h>
569 jermar 35
#include <arch/asm.h>
613 jermar 36
#include <arch/barrier.h>
569 jermar 37
#include <arch/types.h>
38
#include <typedefs.h>
530 jermar 39
 
569 jermar 40
#define ITLB_ENTRY_COUNT        64
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#define DTLB_ENTRY_COUNT        64
42
 
619 jermar 43
/** Page sizes. */
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#define PAGESIZE_8K 0
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#define PAGESIZE_64K    1
46
#define PAGESIZE_512K   2
47
#define PAGESIZE_4M 3
531 jermar 48
 
873 jermar 49
union tlb_context_reg {
50
    __u64 v;
51
    struct {
52
        unsigned long : 51;
53
        unsigned context : 13;      /**< Context/ASID. */
54
    } __attribute__ ((packed));
55
};
56
typedef union tlb_context_reg tlb_context_reg_t;
57
 
530 jermar 58
/** I-/D-TLB Data In/Access Register type. */
59
typedef tte_data_t tlb_data_t;
60
 
569 jermar 61
/** I-/D-TLB Data Access Address in Alternate Space. */
62
union tlb_data_access_addr {
63
    __u64 value;
64
    struct {
65
        __u64 : 55;
66
        unsigned tlb_entry : 6;
67
        unsigned : 3;
68
    } __attribute__ ((packed));
69
};
70
typedef union tlb_data_access_addr tlb_data_access_addr_t;
71
typedef union tlb_data_access_addr tlb_tag_read_addr_t;
418 jermar 72
 
569 jermar 73
/** I-/D-TLB Tag Read Register. */
74
union tlb_tag_read_reg {
75
    __u64 value;
76
    struct {
617 jermar 77
        __u64 vpn : 51;     /**< Virtual Address bits 63:13. */
569 jermar 78
        unsigned context : 13;  /**< Context identifier. */
79
    } __attribute__ ((packed));
80
};
81
typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
613 jermar 82
typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
569 jermar 83
 
617 jermar 84
/** TLB Demap Operation types. */
85
#define TLB_DEMAP_PAGE      0
86
#define TLB_DEMAP_CONTEXT   1
87
 
88
/** TLB Demap Operation Context register encodings. */
89
#define TLB_DEMAP_PRIMARY   0
90
#define TLB_DEMAP_SECONDARY 1
91
#define TLB_DEMAP_NUCLEUS   2
92
 
93
/** TLB Demap Operation Address. */
94
union tlb_demap_addr {
95
    __u64 value;
96
    struct {
97
        __u64 vpn: 51;      /**< Virtual Address bits 63:13. */
98
        unsigned : 6;       /**< Ignored. */
99
        unsigned type : 1;  /**< The type of demap operation. */
100
        unsigned context : 2;   /**< Context register selection. */
101
        unsigned : 4;       /**< Zero. */
102
    } __attribute__ ((packed));
103
};
104
typedef union tlb_demap_addr tlb_demap_addr_t;
105
 
873 jermar 106
/** TLB Synchronous Fault Status Register. */
107
union tlb_sfsr_reg {
108
    __u64 value;
109
    struct {
110
        unsigned long : 39; /**< Implementation dependent. */
111
        unsigned nf : 1;    /**< Nonfaulting load. */
112
        unsigned asi : 8;   /**< ASI. */
113
        unsigned tm : 1;    /**< TLB miss. */
114
        unsigned : 3;
115
        unsigned ft : 5;    /**< Fault type. */
116
        unsigned e : 1;     /**< Side-effect bit. */
117
        unsigned ct : 2;    /**< Context Register selection. */
118
        unsigned pr : 1;    /**< Privilege bit. */
119
        unsigned w : 1;     /**< Write bit. */
120
        unsigned ow : 1;    /**< Overwrite bit. */
121
        unsigned fv : 1;    /**< Fayult Valid bit. */
122
    } __attribute__ ((packed));
123
};
124
typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
125
 
126
/** Read MMU Primary Context Register.
127
 *
128
 * @return Current value of Primary Context Register.
129
 */
130
static inline __u64 mmu_primary_context_read(void)
131
{
132
    return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
133
}
134
 
135
/** Write MMU Primary Context Register.
136
 *
137
 * @param v New value of Primary Context Register.
138
 */
139
static inline void mmu_primary_context_write(__u64 v)
140
{
141
    asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
142
    flush();
143
}
144
 
145
/** Read MMU Secondary Context Register.
146
 *
147
 * @return Current value of Secondary Context Register.
148
 */
149
static inline __u64 mmu_secondary_context_read(void)
150
{
151
    return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
152
}
153
 
154
/** Write MMU Primary Context Register.
155
 *
156
 * @param v New value of Primary Context Register.
157
 */
158
static inline void mmu_secondary_context_write(__u64 v)
159
{
160
    asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
161
    flush();
162
}
163
 
569 jermar 164
/** Read IMMU TLB Data Access Register.
165
 *
166
 * @param entry TLB Entry index.
167
 *
168
 * @return Current value of specified IMMU TLB Data Access Register.
169
 */
170
static inline __u64 itlb_data_access_read(index_t entry)
171
{
172
    tlb_data_access_addr_t reg;
173
 
174
    reg.value = 0;
175
    reg.tlb_entry = entry;
176
    return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
177
}
178
 
617 jermar 179
/** Write IMMU TLB Data Access Register.
180
 *
181
 * @param entry TLB Entry index.
182
 * @param value Value to be written.
183
 */
658 jermar 184
static inline void itlb_data_access_write(index_t entry, __u64 value)
617 jermar 185
{
186
    tlb_data_access_addr_t reg;
187
 
188
    reg.value = 0;
189
    reg.tlb_entry = entry;
190
    asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
191
    flush();
192
}
193
 
569 jermar 194
/** Read DMMU TLB Data Access Register.
195
 *
196
 * @param entry TLB Entry index.
197
 *
198
 * @return Current value of specified DMMU TLB Data Access Register.
199
 */
200
static inline __u64 dtlb_data_access_read(index_t entry)
201
{
202
    tlb_data_access_addr_t reg;
203
 
204
    reg.value = 0;
205
    reg.tlb_entry = entry;
206
    return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
207
}
208
 
617 jermar 209
/** Write DMMU TLB Data Access Register.
210
 *
211
 * @param entry TLB Entry index.
212
 * @param value Value to be written.
213
 */
658 jermar 214
static inline void dtlb_data_access_write(index_t entry, __u64 value)
617 jermar 215
{
216
    tlb_data_access_addr_t reg;
217
 
218
    reg.value = 0;
219
    reg.tlb_entry = entry;
220
    asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
221
    flush();
222
}
223
 
569 jermar 224
/** Read IMMU TLB Tag Read Register.
225
 *
226
 * @param entry TLB Entry index.
227
 *
228
 * @return Current value of specified IMMU TLB Tag Read Register.
229
 */
613 jermar 230
static inline __u64 itlb_tag_read_read(index_t entry)
569 jermar 231
{
232
    tlb_tag_read_addr_t tag;
233
 
234
    tag.value = 0;
235
    tag.tlb_entry = entry;
236
    return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
237
}
238
 
239
/** Read DMMU TLB Tag Read Register.
240
 *
241
 * @param entry TLB Entry index.
242
 *
243
 * @return Current value of specified DMMU TLB Tag Read Register.
244
 */
613 jermar 245
static inline __u64 dtlb_tag_read_read(index_t entry)
569 jermar 246
{
247
    tlb_tag_read_addr_t tag;
248
 
249
    tag.value = 0;
250
    tag.tlb_entry = entry;
251
    return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
252
}
253
 
613 jermar 254
/** Write IMMU TLB Tag Access Register.
255
 *
256
 * @param v Value to be written.
257
 */
258
static inline void itlb_tag_access_write(__u64 v)
259
{
260
    asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
261
    flush();
262
}
263
 
264
/** Write DMMU TLB Tag Access Register.
265
 *
266
 * @param v Value to be written.
267
 */
268
static inline void dtlb_tag_access_write(__u64 v)
269
{
270
    asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
271
    flush();
272
}
273
 
274
/** Write IMMU TLB Data in Register.
275
 *
276
 * @param v Value to be written.
277
 */
278
static inline void itlb_data_in_write(__u64 v)
279
{
280
    asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
281
    flush();
282
}
283
 
284
/** Write DMMU TLB Data in Register.
285
 *
286
 * @param v Value to be written.
287
 */
288
static inline void dtlb_data_in_write(__u64 v)
289
{
290
    asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
291
    flush();
292
}
293
 
873 jermar 294
/** Read ITLB Synchronous Fault Status Register.
295
 *
296
 * @return Current content of I-SFSR register.
297
 */
298
static inline __u64 itlb_sfsr_read(void)
299
{
300
    return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
301
}
302
 
303
/** Write ITLB Synchronous Fault Status Register.
304
 *
305
 * @param v New value of I-SFSR register.
306
 */
307
static inline void itlb_sfsr_write(__u64 v)
308
{
309
    asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
310
    flush();
311
}
312
 
313
/** Read DTLB Synchronous Fault Status Register.
314
 *
315
 * @return Current content of D-SFSR register.
316
 */
317
static inline __u64 dtlb_sfsr_read(void)
318
{
319
    return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
320
}
321
 
322
/** Write DTLB Synchronous Fault Status Register.
323
 *
324
 * @param v New value of D-SFSR register.
325
 */
326
static inline void dtlb_sfsr_write(__u64 v)
327
{
328
    asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
329
    flush();
330
}
331
 
332
/** Read DTLB Synchronous Fault Address Register.
333
 *
334
 * @return Current content of D-SFAR register.
335
 */
336
static inline __u64 dtlb_sfar_read(void)
337
{
338
    return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
339
}
340
 
617 jermar 341
/** Perform IMMU TLB Demap Operation.
342
 *
343
 * @param type Selects between context and page demap.
344
 * @param context_encoding Specifies which Context register has Context ID for demap.
345
 * @param page Address which is on the page to be demapped.
346
 */
347
static inline void itlb_demap(int type, int context_encoding, __address page)
348
{
349
    tlb_demap_addr_t da;
350
    page_address_t pg;
351
 
352
    da.value = 0;
353
    pg.address = page;
354
 
355
    da.type = type;
356
    da.context = context_encoding;
357
    da.vpn = pg.vpn;
358
 
359
    asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);
360
    flush();
361
}
362
 
363
/** Perform DMMU TLB Demap Operation.
364
 *
365
 * @param type Selects between context and page demap.
366
 * @param context_encoding Specifies which Context register has Context ID for demap.
367
 * @param page Address which is on the page to be demapped.
368
 */
369
static inline void dtlb_demap(int type, int context_encoding, __address page)
370
{
371
    tlb_demap_addr_t da;
372
    page_address_t pg;
373
 
374
    da.value = 0;
375
    pg.address = page;
376
 
377
    da.type = type;
378
    da.context = context_encoding;
379
    da.vpn = pg.vpn;
380
 
381
    asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
382
    flush();
383
}
384
 
863 jermar 385
extern void fast_instruction_access_mmu_miss(void);
386
extern void fast_data_access_mmu_miss(void);
387
extern void fast_data_access_protection(void);
388
 
418 jermar 389
#endif