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418 jermar 1
/*
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 * Copyright (C) 2005 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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#ifndef __sparc64_TLB_H__
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#define __sparc64_TLB_H__
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#include <arch/mm/tte.h>
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#include <arch/asm.h>
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#include <arch/types.h>
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#include <typedefs.h>
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#define ITLB_ENTRY_COUNT        64
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#define DTLB_ENTRY_COUNT        64
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/** I-MMU ASIs. */
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#define ASI_IMMU            0x50
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#define ASI_IMMU_TSB_8KB_PTR_REG    0x51    
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#define ASI_IMMU_TSB_64KB_PTR_REG   0x52
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#define ASI_ITLB_DATA_IN_REG        0x54
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#define ASI_ITLB_DATA_ACCESS_REG    0x55
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#define ASI_ITLB_TAG_READ_REG       0x56
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#define ASI_IMMU_DEMAP          0x57
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/** Virtual Addresses within ASI_IMMU. */
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#define VA_IMMU_TAG_TARGET      0x0 /**< IMMU tag target register. */
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#define VA_IMMU_SFSR            0x18    /**< IMMU sync fault status register. */
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#define VA_IMMU_TSB_BASE        0x28    /**< IMMU TSB base register. */
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#define VA_IMMU_TAG_ACCESS      0x30    /**< IMMU TLB tag access register. */
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/** D-MMU ASIs. */
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#define ASI_DMMU            0x58
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#define ASI_DMMU_TSB_8KB_PTR_REG    0x59    
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#define ASI_DMMU_TSB_64KB_PTR_REG   0x5a
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#define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b
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#define ASI_DTLB_DATA_IN_REG        0x5c
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#define ASI_DTLB_DATA_ACCESS_REG    0x5d
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#define ASI_DTLB_TAG_READ_REG       0x5e
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#define ASI_DMMU_DEMAP          0x5f
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/** Virtual Addresses within ASI_DMMU. */
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#define VA_DMMU_TAG_TARGET      0x0 /**< DMMU tag target register. */
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#define VA_PRIMARY_CONTEXT_REG      0x8 /**< DMMU primary context register. */
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#define VA_SECONDARY_CONTEXT_REG    0x10    /**< DMMU secondary context register. */
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#define VA_DMMU_SFSR            0x18    /**< DMMU sync fault status register. */
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#define VA_DMMU_SFAR            0x20    /**< DMMU sync fault address register. */
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#define VA_DMMU_TSB_BASE        0x28    /**< DMMU TSB base register. */
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#define VA_DMMU_TAG_ACCESS      0x30    /**< DMMU TLB tag access register. */
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#define VA_DMMU_VA_WATCHPOINT_REG   0x38    /**< DMMU VA data watchpoint register. */
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#define VA_DMMU_PA_WATCHPOINT_REG   0x40    /**< DMMU PA data watchpoint register. */
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/** I-/D-TLB Data In/Access Register type. */
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typedef tte_data_t tlb_data_t;
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/** I-/D-TLB Data Access Address in Alternate Space. */
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union tlb_data_access_addr {
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    __u64 value;
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    struct {
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        __u64 : 55;
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        unsigned tlb_entry : 6;
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        unsigned : 3;
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    } __attribute__ ((packed));
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};
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typedef union tlb_data_access_addr tlb_data_access_addr_t;
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typedef union tlb_data_access_addr tlb_tag_read_addr_t;
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/** I-/D-TLB Tag Read Register. */
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union tlb_tag_read_reg {
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    __u64 value;
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    struct {
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        __u64 va : 51;      /**< Virtual Address. */
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        unsigned context : 13;  /**< Context identifier. */
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    } __attribute__ ((packed));
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};
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typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
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/** Read IMMU TLB Data Access Register.
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 *
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 * @param entry TLB Entry index.
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 *
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 * @return Current value of specified IMMU TLB Data Access Register.
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 */
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static inline __u64 itlb_data_access_read(index_t entry)
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{
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    tlb_data_access_addr_t reg;
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    reg.value = 0;
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    reg.tlb_entry = entry;
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    return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
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}
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/** Read DMMU TLB Data Access Register.
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 *
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 * @param entry TLB Entry index.
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 *
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 * @return Current value of specified DMMU TLB Data Access Register.
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 */
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static inline __u64 dtlb_data_access_read(index_t entry)
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{
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    tlb_data_access_addr_t reg;
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    reg.value = 0;
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    reg.tlb_entry = entry;
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    return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
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}
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/** Read IMMU TLB Tag Read Register.
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 *
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 * @param entry TLB Entry index.
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 *
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 * @return Current value of specified IMMU TLB Tag Read Register.
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 */
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static inline __u64 itlb_tag_read(index_t entry)
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{
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    tlb_tag_read_addr_t tag;
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    tag.value = 0;
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    tag.tlb_entry = entry;
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    return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
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}
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/** Read DMMU TLB Tag Read Register.
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 *
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 * @param entry TLB Entry index.
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 *
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 * @return Current value of specified DMMU TLB Tag Read Register.
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 */
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static inline __u64 dtlb_tag_read(index_t entry)
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{
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    tlb_tag_read_addr_t tag;
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    tag.value = 0;
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    tag.tlb_entry = entry;
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    return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
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}
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#endif